Electroless gold plating method for forming inductor structures
First Claim
1. A method of fabricating a gold containing integrated wiring structure for an integrated circuit comprising:
- a) forming a first insulating layer over a substrate;
b) forming a barrier layer containing nickel using an electroless deposition process over said first insulating layer;
c) forming a gold conductor layer using an electroless deposition process over said barrier layer;
said gold conductor layer and said barrier layer comprise a first conductor layer;
d) forming a planarization layer over said gold conductor layer;
e) forming a core metal layer composed of Fe--Co alloy using an electroless deposition process over the planarization layer;
said core metal layer is formed by an electroless plating process having a solution comprising;
KAu(CN)2 with a concentration between about 4 and 6 g/L, KCN with a concentration between about 7 and 9 g/L, NaOH with a concentration between about 18 and 22 g/L, Na2 EDTA with a concentration between about 13 and 17 g/L, NaBH4 with a concentration between about 23 and 27 g/L, and at a temperature between about 87 and 93°
C.
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Accused Products
Abstract
The present invention provides a method of manufacturing an inductor element 46 using an electroless Au plating solution. The invention has three embodiments for forming the inductor. In the first embodiment, a first insulating layer 30 is formed over a semiconductor structure 10 20. An adhesion layer 34 composed of polysilicon is formed over the first insulating layer 30. A first barrier layer 36 comprised of Ni is selectively formed using an Ni electroless plating process over the adhesion layer 34. In an important step, a gold layer 40 is electroless plated over the first barrier layer 36 using an Au electroless plating process. A second barrier layer 44 is formed over the gold layer 40 using an electroless Ni deposition technique. A planarization layer is formed over the second barrier layer. A novel core metal layer composed of a Fe--Co alloy is electroless plated over the planarization layer. The second and third embodiments vary in the process of defining the gold electroless inductor by forming the inductor in a trench. The gold electroless inductor 46 can withstand high current densities without suffering from electromigration effects and is highly corrosion resistant.
210 Citations
25 Claims
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1. A method of fabricating a gold containing integrated wiring structure for an integrated circuit comprising:
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a) forming a first insulating layer over a substrate; b) forming a barrier layer containing nickel using an electroless deposition process over said first insulating layer; c) forming a gold conductor layer using an electroless deposition process over said barrier layer;
said gold conductor layer and said barrier layer comprise a first conductor layer;d) forming a planarization layer over said gold conductor layer; e) forming a core metal layer composed of Fe--Co alloy using an electroless deposition process over the planarization layer;
said core metal layer is formed by an electroless plating process having a solution comprising;
KAu(CN)2 with a concentration between about 4 and 6 g/L, KCN with a concentration between about 7 and 9 g/L, NaOH with a concentration between about 18 and 22 g/L, Na2 EDTA with a concentration between about 13 and 17 g/L, NaBH4 with a concentration between about 23 and 27 g/L, and at a temperature between about 87 and 93°
C. - View Dependent Claims (2, 3, 4)
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5. A method of fabrication an inductor element for a semiconductor device;
- comprising the steps of;
a) forming a first insulating layer over a semiconductor structure; b) forming and patterning an adhesion layer composed of polysilicon over said first insulating layer; c) selectively forming a first barrier layer comprised of Ni using an Ni electroless plating solution over said adhesion layer; d) electroless plating a gold layer over said first barrier layer using an Au electroless plating bath; e) forming a second barrier layer composed of Ni over said gold layer using an electroless Ni deposition technique;
said first barrier layer, said gold layer, said second barrier layer comprise a first inductor element;f) forming a planarization layer over said second barrier layer; g) forming a core metal layer composed of Fe--Co using an electroless deposition process over said planarization layer. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12)
- comprising the steps of;
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13. A method of fabrication an inductor element for a semiconductor device;
- comprising the steps of;
a) forming a first insulating layer over a semiconductor structure; b) forming and patterning an adhesion layer composed of polysilicon over said first insulating layer;
said adhesion layer composed of a doped polysilicon having a thickness in a range of between about 1800 and 2200 Å and
a doping concentration in a range of between about 1E14 Atoms/cm3 and 1E16 Atoms/cm3 ;c) activating said adhesion layer using an Pd electroless activating bath forming an activated adhesion layer over said adhesion layer; d) selectively forming a first barrier layer comprised of Ni using an Ni electroless plating solution over said adhesion layer;
said first barrier layer containing nickel is formed by an electroless plating process and said first barrier layer has a Ni concentration between about 90 and 100 wt % and P concentration between about 0 and 10 wt %;e) electroless plating a gold layer over said first barrier layer using an Au electroless plating process; f) activating said gold layer using a Pd activating process; g) forming a second barrier layer over said gold layer using an electroless Ni deposition technique;
said first barrier layer, said gold layer, said second barrier layer comprise a first inductor element;h) forming a planarization layer over said second barrier layer; i) forming a core metal layer composed of Fe--Co using an electroless deposition process over said planarization layer;
said core metal layer composed of a Fe--Co alloy having a thickness in a range of between about 8000 and 12000 Å
;
said core metal layer is formed by an electroless plating process having a solution comprising;
KAu(CN)2 with a concentration between about 4 and 6 g/L, KCN with a concentration between about 7 and 9 g/L, NaOH with a concentration between about 18 and 22 g/L, Na2 EDTA with a concentration between about 13 and 17 g/L, NaBH4 with a concentration between about 23 and 27 g/L, and at a temperature between about 87 and 93°
C. - View Dependent Claims (14)
- comprising the steps of;
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15. A method of fabrication an inductor for a semiconductor device;
- comprising the steps of;
a) forming first insulating layer over a semiconductor structure; b) patterning said first insulating layer forming at least a trench;
said first insulating layer having sidewalls defining said trench;c) forming an adhesion layer composed of polysilicon over said first insulating layer; d) chemically mechanically polishing said adhesion layer leaving said adhesion layer lining said sidewalls of said first insulating layer in said trench; e) forming a first barrier layer comprised of Ni using an Ni electroless plating solution over said adhesion layer in said trench; f) electroless plating a gold layer over said first barrier layer using an Au electroless plating process filling said trench; g) forming a second barrier layer over said gold layer using an electroless Ni deposition technique;
said first barrier layer, said gold layer, said second barrier layer comprise a first inductor element;h) forming a planarization layer over said second barrier layer; and i) forming a core metal layer over said planarization layer. - View Dependent Claims (16, 17, 18, 19, 20)
- comprising the steps of;
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21. A method of fabrication an inductor for a semiconductor device;
- comprising the steps of;
a) forming first insulating layer over a semiconductor structure; b) patterning said first insulating layer forming at least a trench;
said first insulating layer having sidewalls defining said trench;c) forming an adhesion layer composed of polysilicon over said first insulating layer;
said adhesion layer composed of a doped polysilicon having a thickness in a range of between about 1000 and 2200 Å
;d) chemically mechanically polishing said adhesion layer leaving said adhesion layer lining said sidewalls of said first insulating layer in said trench; e) activating said adhesion layer using an Pd electroless activating bath; f) forming a first barrier layer comprised of Ni using an Ni electroless plating solution over said adhesion layer in said trench; g) electroless plating a gold layer over said first barrier layer using an Au electroless plating process filling said trench; h) activating said gold layer using a Pd activating bath; i) forming a second barrier layer over said gold layer using an electroless Ni deposition technique;
said first barrier layer, said gold layer, said second barrier layer comprise a first inductor element;j) forming a planarization layer over said second barrier layer; k) forming a core metal layer over said planarization layer;
said core metal layer composed of a Fe--Co alloy having a thickness in a range of between about 8000 and 10,000 Å
;
said core metal layer is formed by an electroless plating process having a solution comprising;
KAu(CN)2 with a concentration between about 4 and 6 g/L, KCN with a concentration between about 7 and 9 g/L, NaOH with a concentration between about 18 and 22 g/L, Na2 EDTA with a concentration between about 13 and 17 g/L, NaBH4 with a concentration between about 23 and 27 g/L, and at a temperature between about 87 and 93°
C.
- comprising the steps of;
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22. A method of fabrication an inductor element for a semiconductor device;
- comprising the steps of;
a) forming a first insulating layer over a substrate; b) forming a first photoresist layer over said first insulating layer;
said first photoresist layer having a first opening;c) forming a trench in said first insulating layer using said first photoresist layer as a mask; d) removing said first photoresist layer; e) forming a first barrier layer comprised of Ni using an electroless deposition technique over said adhesion layer in said bottom of said trench; f) plating a gold layer over said first barrier layer using an electroless deposition technique filling said trench;
said first barrier layer and said gold layer comprising a first inductor element;g) forming a planarization layer over said gold layer; h) forming a core metal layer over said planarization layer. - View Dependent Claims (23, 24)
- comprising the steps of;
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25. A method of fabrication an inductor element for a semiconductor device;
- comprising the steps of;
a) forming a first nitride layer over a semiconductor structure; b) forming a first insulating layer over said first nitride layer; c) forming a first photoresist layer over said first insulating layer;
said first photoresist layer having a first opening;d) forming a trench in said first insulating layer using said first photoresist layer as a mask;
said trench having a depth in a range of between about 16,000 and 20,000 Å
;e) activating said first insulating layer by implanting Pd ions into said first insulating layer in the bottom said trench;
the implantation of said first insulating layer performed by implanting Pd ions at an energy in a range of between about 30 Kev and 50 Kev and more preferably about 40 Kev and said first insulating layer having a Pd concentration in a range of between about 1E15 and 1E16 atoms/CC and more preferably about 5E15 atoms/CC;f) removing said first photoresist layer; g) forming a first barrier layer comprised of Ni using an electroless deposition technique over said adhesion layer in said bottom of said trench; h) plating a gold layer over said first barrier layer using an electroless deposition technique filling said trench;
said first barrier layer and said gold layer comprising a first inductor element;i) forming a planarization layer over said gold layer; j) forming a core metal layer over said planarization layer;
said core metal layer composed of a Fe--Co alloy having a thickness in a range of between about 8000 and 12,000 Å
;
said core metal layer is formed by an electroless plating process having a solution comprising;
KAu(CN)2 with a concentration between about 4 and 6 g/L, KCN with a concentration between about 7 and 9 g/L, NaOH with a concentration between about 18 and 22 g/L, Na2 EDTA with a concentration between about 13 and 17 g/L, NaBH4 with a concentration between about 23 and 27 g/L, and at a temperature between about 87 and 93°
C.
- comprising the steps of;
Specification