Method of producing semiconductor devices and method of evaluating the same

• US 6,031,246 A
• Filed: 12/18/1998
• Issued: 02/29/2000
• Est. Priority Date: 03/17/1994
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Hamada, Makoto, Shono, Ken
• Primary Examiner(s): CRANE, SARA W
• Application Number:
  US09/215,625
• Time in Patent Office: 438 Days
• Field of Search: 257/48, 257/395, 257/401, 257/396, 257/399, 257/919, 257/921, 257/925, 438/17, 324/537
• US Class Current: 257/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A simulation method capable of efficiently evaluating reliability of gate oxide films formed on the elements within short periods of time to evaluate characteristics of a semiconductor device made up of elements of any size and any number. In a semiconductor device having transistors formed thereon, a pattern for evaluating characteristics of a semiconductor device characterized in that gate area portions, gate bird'"'"'s-beak portions and LOCOS bird'"'"'s-beak portions, are factors affecting the insulation breakdown of the gate oxide film, are rendered to be variable, so that the shapes of these portions can be handled as independent parameters.

Claims

1. A method of evaluating characteristics of a semiconductor device characterized in that evaluation is carried out in accordance with a simulation performed by using a polynomial which includes physical lengths or sizes as parameters of gate area portions, gate bird'"'"'s-beak portions and peripheral bird'"'"'s-beak portions related to transistors that are formed on the substrate of the semiconductor device and in which predetermined coefficients are imparted to the individual parameters.

2. A method of evaluating characteristics of a semiconductor of said semiconductor device according to claim 1, wherein said evaluation of said semiconductor device is carried out so as to investigate the reliability of the transistor by evaluating either QBD characteristics based on the total amount of electric charge until the insulation breakdown occurs in the transistor as a result of executing an insulation breakdown of executing an insulation breakdown testing, or TDDB characteristics based on the total time up to that moment.

3. A method of evaluating characteristics of a semiconductor device according to claim 2, wherein a plurality of different patterns for evaluating characteristics are prepared, predetermined transistors for testing are formed by using said patterns for evaluating characteristics, said plurality of testing transistors thus obtained are subjected to a predetermined insulation breakdown testing, the obtained evaluation data and parameters in said testing transistors are substituted in said polynomial, and coefficients of said parameters in said polynomial are calculated according to a statistical method.

4. A method of designing a semiconductor device with evaluating characteristics of a semiconductor device in relation to transistors formed on a substrate of said semiconductor device in accordance with a simulation performed by using a polynomial which includes physical lengths or sizes as parameters of gate area portions, gate bird'"'"'s-beak portions and peripheral bird'"'"'s-beak portions of said transistors as parameters and in which predetermined coefficients are imparted to the individual parameters, comprising:

a step for forming predetermined testing transistors by using plural kinds of patterns for evaluating characteristics, which patterns are prepared beforehand therefor;

a step for executing preliminary insulation breakdown testing for said plurality kinds of testing transistors that are formed;

a step for calculating coefficients of parameters in a polynomial by substituting evaluation data obtained by said preliminary insulation breakdown testing and the parameters in said testing transistors for said polynomial;

a step for subjecting a prototype transistor having predetermined design conditions to the insulation breakdown testing by using said polynomial for which said coefficients are determined;

a step for evaluating the characteristics of said prototype transistor relying upon the results obtained by said insulation breakdown testing; and

a step for changing the constitution of portions in a transistor to be actually formed in said semiconductor device, which portions correspond to the portions that are likely to undergo insulation breakdown in said prototype transistor relying upon the results of evaluation of characteristics.

5. A method of producing a semiconductor device according to claim 4, wherein transistors are formed on a semiconductor substrate in accordance with design conditions for major portions of the transistors, wherein said design conditions are set based upon said designing method.