Enhancing DMOS device ruggedness by reducing transistor parasitic resistance and by inducing breakdown near gate runners and termination area
First Claim
1. A vertical DMOS power device includes a core cell area and a gate runner area formed in a semiconductor substrate with a top surface and a bottom surface, said power device comprisinga plurality of vertical DMOS transistor cells disposed in said core cell area wherein each transistor cell includes a drain of a first conductivity type disposed at said bottom surface of said substrate;
- each of said transistor cells further includes a trench surrounding said cell having a polysilicon disposed in said trench defining a gate for said transistor dell;
each of said transistor cells further includes a source region of said first conductivity type disposed in said substrate near said gate;
each of said transistor cells further includes a body region of a second conductivity type disposed in said substrate between said gate wherein said body region defining a vertical current channel along said trench between said source and said drain;
a plurality of trenched polysislicon fingers extended from said trenched gate to said gate runner area;
a plurality of ruggedness enhancing body dopant regions of said second conductivity type disposed in said substrate between said trenched polysilicon fingers in said gate runner area and in a termination area near a periphery of said substrate wherein each of said ruggedness enhancing body dopant regions further includes a breakdown-inducing-regions disposed at bottom of said body dopant region at a depth below said trenched gate-extension fingers having a higher dopant concentration of said second conductivity type for inducing a breakdown therein; and
a trenched gate runner includes a trench with a gate-runner polysilicon therein, said trenched gate runner intersecting said polysilicon fingers, and said gate runner having a width substantial greater than said polysilicon fingers provided for forming a gate contact therein.
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Abstract
This invention discloses a vertical DMOS power device formed in a semiconductor substrate with a top surface and a bottom surface. The power device includes a core cell area and a gate runner area. The power device includes a plurality of vertical DMOS transistor cells disposed in the core cell area wherein each transistor cell includes a drain of a first conductivity type disposed at the bottom surface of the substrate. Each of the DMOS transistor cells further includes a trench surrounding the cell having a polysilicon disposed in the trench defining a gate for the transistor cell. Each of the transistor cells further includes a source region of the first conductivity type disposed in the substrate near the gate. Each of the transistor cells further includes a body region of a second conductivity type disposed in the substrate between the gate wherein the body region defining a vertical current channel along the trench between the source and the drain. The power device further includes a plurality of trenched polysilicon fingers extended from the trenched gate to the gate runner area. The power device further includes a plurality of ruggedness enhancing body dopant regions of the second conductivity type disposed in the substrate between the trenched polysilicon fingers and in a termination, each of the ruggedness enhancing body dopant regions further includes a breakdown-inducing-regions disposed at bottom of the body dopant region at a depth below the trenched gate-extension fingers having a higher dopant concentration of the second conductivity type for inducing a breakdown therein. In a preferred embodiment, each of the vertical DMOS further includes a deep high concentration dopant region disposed in the body region below the source having a higher dopant concentration than the body region.
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Citations
15 Claims
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1. A vertical DMOS power device includes a core cell area and a gate runner area formed in a semiconductor substrate with a top surface and a bottom surface, said power device comprising
a plurality of vertical DMOS transistor cells disposed in said core cell area wherein each transistor cell includes a drain of a first conductivity type disposed at said bottom surface of said substrate; -
each of said transistor cells further includes a trench surrounding said cell having a polysilicon disposed in said trench defining a gate for said transistor dell; each of said transistor cells further includes a source region of said first conductivity type disposed in said substrate near said gate; each of said transistor cells further includes a body region of a second conductivity type disposed in said substrate between said gate wherein said body region defining a vertical current channel along said trench between said source and said drain; a plurality of trenched polysislicon fingers extended from said trenched gate to said gate runner area; a plurality of ruggedness enhancing body dopant regions of said second conductivity type disposed in said substrate between said trenched polysilicon fingers in said gate runner area and in a termination area near a periphery of said substrate wherein each of said ruggedness enhancing body dopant regions further includes a breakdown-inducing-regions disposed at bottom of said body dopant region at a depth below said trenched gate-extension fingers having a higher dopant concentration of said second conductivity type for inducing a breakdown therein; and a trenched gate runner includes a trench with a gate-runner polysilicon therein, said trenched gate runner intersecting said polysilicon fingers, and said gate runner having a width substantial greater than said polysilicon fingers provided for forming a gate contact therein. - View Dependent Claims (2, 3, 4, 5)
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6. A vertical DMOS power device includes a core cell area and a gate runner area formed in a semiconductor substrate with a top surface and a bottom surface, said power device comprising
a plurality of vertical DMOS transistor cells disposed in said core cell area wherein each transistor cell includes a drain of a first conductivity type disposed at said bottom surface of said substrate; -
each of said transistor cells further includes a trench surrounding said cell having a polysilicon disposed in said trench defining a gate for said transistor dell; each of said transistor cells further includes a source region of said first conductivity type disposed in said substrate near said gate; each of said transistor cells further includes a body region of a second conductivity type disposed in said substrate between said gate wherein said body region defining a vertical current channel along said trench between said source and said drain; a plurality of trenched polysislicon fingers extended from selected gates among said trenched gates to said gate runner area thus providing several wide areas between said polysilicon fingers; a plurality of ruggedness enhancing body dopant regions of said second conductivity type disposed in said substrate in said wide areas between said trenched polysilicon fingers each of said ruggedness enhancing body dopant regions further includes a breakdown-inducing-regions disposed at bottom of said body dopant region at a depth below said trenched gate-extension fingers having a higher dopant concentration of said second conductivity type for inducing a breakdown therein; and each of said polysilicon fingers further includes an enlarged trench-end disposed at an end of each polysilicon fingers having an enlarged trench with a gate contact polysilicon disposed therein provided for forming a gate contact thereon. - View Dependent Claims (7, 8, 9, 10)
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11. A semiconductor power device formed in a semiconductor substrate with a top surface and a bottom surface, said power device comprising a core cell area and a gate runner area, said core cell are includes a plurality of transistor cells each includes a drin disposed at said bottom surface, a source region and a body region in said substrate and a trenched gate disposed in a trench opened from said top surface, said power device further comprising
a plurality of trenched gate-extension fingers extended from said trenched gates to said gate runner area; - and
a plurality of ruggedness enhancing body dopant regions disposed in said substrate between said gate-extension fingers, each of said ruggedness enhancing body dopant regions further includes a breakdown-inducing-regions disposed at bottom of said body dopant region at a depth below said trenched gate-extension fingers; each of said gate-extension fingers further includes an enlarged trench-end disposed at an end of each gate-extension fingers having an enlarged trench with a gate contact polysilicon disposed therein provided for forming a gate contact thereon. - View Dependent Claims (12, 13, 14, 15)
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Specification