Enhancing DMOS device ruggedness by reducing transistor parasitic resistance and by inducing breakdown near gate runners and termination area

• US 6,031,265 A
• Filed: 10/16/1997
• Issued: 02/29/2000
• Est. Priority Date: 10/16/1997
• Status: Expired due to Term

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: MagePower Semiconductor Corporation
• Inventors: Hshieh, Fwu-Iuan
• Primary Examiner(s): Monin, Jr., Donald L.
• Application Number:
  US08/951,622
• Time in Patent Office: 866 Days
• Field of Search: 257/328, 257/330, 257/331, 257/334, 257/339, 257/355, 257/356
• US Class Current: 257/334
• CPC Class Codes: H01L 29/0626 with a localised breakdown region, e.g. built-in avalanching region in self-protected thyristors H01L29/7424
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

This invention discloses a vertical DMOS power device formed in a semiconductor substrate with a top surface and a bottom surface. The power device includes a core cell area and a gate runner area. The power device includes a plurality of vertical DMOS transistor cells disposed in the core cell area wherein each transistor cell includes a drain of a first conductivity type disposed at the bottom surface of the substrate. Each of the DMOS transistor cells further includes a trench surrounding the cell having a polysilicon disposed in the trench defining a gate for the transistor cell. Each of the transistor cells further includes a source region of the first conductivity type disposed in the substrate near the gate. Each of the transistor cells further includes a body region of a second conductivity type disposed in the substrate between the gate wherein the body region defining a vertical current channel along the trench between the source and the drain. The power device further includes a plurality of trenched polysilicon fingers extended from the trenched gate to the gate runner area. The power device further includes a plurality of ruggedness enhancing body dopant regions of the second conductivity type disposed in the substrate between the trenched polysilicon fingers and in a termination, each of the ruggedness enhancing body dopant regions further includes a breakdown-inducing-regions disposed at bottom of the body dopant region at a depth below the trenched gate-extension fingers having a higher dopant concentration of the second conductivity type for inducing a breakdown therein. In a preferred embodiment, each of the vertical DMOS further includes a deep high concentration dopant region disposed in the body region below the source having a higher dopant concentration than the body region.

Claims

1. A vertical DMOS power device includes a core cell area and a gate runner area formed in a semiconductor substrate with a top surface and a bottom surface, said power device comprising

a plurality of vertical DMOS transistor cells disposed in said core cell area wherein each transistor cell includes a drain of a first conductivity type disposed at said bottom surface of said substrate;

each of said transistor cells further includes a trench surrounding said cell having a polysilicon disposed in said trench defining a gate for said transistor dell;

each of said transistor cells further includes a source region of said first conductivity type disposed in said substrate near said gate;

each of said transistor cells further includes a body region of a second conductivity type disposed in said substrate between said gate wherein said body region defining a vertical current channel along said trench between said source and said drain;

a plurality of trenched polysislicon fingers extended from said trenched gate to said gate runner area;

a plurality of ruggedness enhancing body dopant regions of said second conductivity type disposed in said substrate between said trenched polysilicon fingers in said gate runner area and in a termination area near a periphery of said substrate wherein each of said ruggedness enhancing body dopant regions further includes a breakdown-inducing-regions disposed at bottom of said body dopant region at a depth below said trenched gate-extension fingers having a higher dopant concentration of said second conductivity type for inducing a breakdown therein; and

a trenched gate runner includes a trench with a gate-runner polysilicon therein, said trenched gate runner intersecting said polysilicon fingers, and said gate runner having a width substantial greater than said polysilicon fingers provided for forming a gate contact therein.

2. The vertical DMOS power device of claim 1 wherein:

said trench gate runner having a width of about two to three micrometers and said polysilicon fingers having a width of about one micrometer.

3. The vertical DMOS power device of claim 1 wherein:

said first conductivity type is a N-type conductivity and said vertical DMOS transistor cells are N-channel DMOS cells.

4. The vertical DMOS power device of claim 1 wherein:

said first conductivity type is a P-type conductivity and said vertical DMOS transistor cells are P-channel DMOS cells.

5. The vertical DMOS power device of claim 1 wherein:

said breakdown inducing regions between said trenched polysilicon fingers are in electrical contact with each other through a deep body dopant region underneath sand polysilicon fingers thus constituting an integrated ruggedness enhancing body dopant regions in said gate runner areas.

6. A vertical DMOS power device includes a core cell area and a gate runner area formed in a semiconductor substrate with a top surface and a bottom surface, said power device comprising

a plurality of vertical DMOS transistor cells disposed in said core cell area wherein each transistor cell includes a drain of a first conductivity type disposed at said bottom surface of said substrate;

each of said transistor cells further includes a trench surrounding said cell having a polysilicon disposed in said trench defining a gate for said transistor dell;

each of said transistor cells further includes a source region of said first conductivity type disposed in said substrate near said gate;

each of said transistor cells further includes a body region of a second conductivity type disposed in said substrate between said gate wherein said body region defining a vertical current channel along said trench between said source and said drain;

a plurality of trenched polysislicon fingers extended from selected gates among said trenched gates to said gate runner area thus providing several wide areas between said polysilicon fingers;

a plurality of ruggedness enhancing body dopant regions of said second conductivity type disposed in said substrate in said wide areas between said trenched polysilicon fingers each of said ruggedness enhancing body dopant regions further includes a breakdown-inducing-regions disposed at bottom of said body dopant region at a depth below said trenched gate-extension fingers having a higher dopant concentration of said second conductivity type for inducing a breakdown therein; and

each of said polysilicon fingers further includes an enlarged trench-end disposed at an end of each polysilicon fingers having an enlarged trench with a gate contact polysilicon disposed therein provided for forming a gate contact thereon.

7. The vertical DMOS power device of claim 6 wherein:

said body region further includes a shallow high concentration body dopant region disposed near said top surface in said body region for reducing a contact resistance of said DMOS power device.

8. The vertical DMOS power device of claim 6 wherein:

each of said enlarged trenched-ends having a length and width of about two to three micrometers and said polysilicon fingers having a width of about one micrometer.

9. The vertical DMOS power device of claim 6 wherein:

said first conductivity type is a N-type conductivity and said vertical DMOS transistor cells are N-channel DMOS cells.

10. The vertical DMOS power device of claim 6 wherein:

said breakdown inducing regions disposed in said wide areas between said trenched polysilicon fingers are provided with a width substantially greater than a width of said transistor cells for further improving a ruggedness of said power device.

11. A semiconductor power device formed in a semiconductor substrate with a top surface and a bottom surface, said power device comprising a core cell area and a gate runner area, said core cell are includes a plurality of transistor cells each includes a drin disposed at said bottom surface, a source region and a body region in said substrate and a trenched gate disposed in a trench opened from said top surface, said power device further comprising

a plurality of trenched gate-extension fingers extended from said trenched gates to said gate runner area;

and

a plurality of ruggedness enhancing body dopant regions disposed in said substrate between said gate-extension fingers, each of said ruggedness enhancing body dopant regions further includes a breakdown-inducing-regions disposed at bottom of said body dopant region at a depth below said trenched gate-extension fingers;

each of said gate-extension fingers further includes an enlarged trench-end disposed at an end of each gate-extension fingers having an enlarged trench with a gate contact polysilicon disposed therein provided for forming a gate contact thereon.

12. The power device of claim 11 wherein:

each of said enlarged trenched-ends having a length and width of about two to three micrometers and said gate-extension fingers having a width of about one micrometer.

13. The vertical DMOS power device of claim 11 wherein:

said source regions of said transistor cells are of a first conductivity type and said body regions are of a second conductivity type and said first conductivity type is a N-type conductivity and said vertical DMOS transistor cells are N-channel DMOS cells.

14. The vertical DMOS power device of claim 11 wherein:

said source regions of said transistor cells are of a first conductivity type and said body regions are of a second conductivity type and said first conductivity type is a P-type conductivity and said vertical DMOS transistor cells are P-channel DMOS cells.

15. The power device of claim 11 wherein:

said plurality of trenched gate-extension fingers extended from selected gates among said trenched gates to said gate runner area thus providing several wide areas between said gate-extension fingers; and

said breakdown inducing regions disposed in said wide areas between said trenched polysilicon fingers are provided with a width substantially greater than a width of said transistor cells for further improving a ruggedness of said power device.