All-metal, giant magnetoresistive, solid-state component

• US 6,031,273 A
• Filed: 12/08/1998
• Issued: 02/29/2000
• Est. Priority Date: 05/02/1996
• Status: Expired due to Term

• Current Assignee: Integrated MagnetoElectronics Corporation
• Original Assignee: Integrated MagnetoElectronics Corporation
• Inventors: Torok, E. James, Spitzer, Richard
• Primary Examiner(s): PATIDAR, JAY M
• Application Number:
  US09/208,628
• Time in Patent Office: 448 Days
• Field of Search: 324/252, 324/249, 338/32 R, 360/110, 360/111, 360/113, 365/171, 365/230.06, 365/158, 365/173, 365/97, 257/295, 257/421-427, 257/52, 257/359
• US Class Current: 257/421
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 25/00 Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
• CPC Class Codes: G01R 33/093 using multilayer structures, e.g. giant magnetoresistance sensors thin magnetic films H01F10/00
• CPC Class Codes: G11C 11/14 using thin-film elements
• CPC Class Codes: G11C 11/15 using multiple magnetic layers G11C11/155 takes precedence
• CPC Class Codes: H01F 10/3268 the exchange coupling being asymmetric, e.g. by use of additional pinning, by using antiferromagnetic or ferromagnetic coupling interface, i.e. so-called spin-valve [SV] structure, e.g. NiFe/Cu/NiFe/FeMn
• CPC Class Codes: H01F 10/3281 only by use of asymmetry of the magnetic film pair itself, i.e. so-called pseudospin valve [PSV] structure, e.g. NiFe/Cu/Co
• CPC Class Codes: H03K 19/166 using transfluxors
• CPC Class Codes: H10B 61/20 comprising components having three or more electrodes, e.g. transistors

Abstract

A solid-state component is described which includes a network of thin-film elements. At least one thin-film element exhibits giant magnetoresistance. The network has a plurality of nodes, each of which represents a direct electrical connection between two of the thin-film elements. First and second ones of the plurality of nodes comprise power terminals. Third and fourth ones of the plurality of nodes comprise an output. A first conductor is inductively coupled to the at least one thin-film element for applying a first magnetic field thereto.

Claims

1. A logic gate comprising:

a plurality of solid-state components, each of the solid-state components comprising;

a network of thin-film elements, at least one thin-film element exhibiting giant magnetoresistance, the network having a plurality of nodes, each node representing a direct electrical connection between two of the thin-film elements, first and second ones of the plurality of nodes comprising power terminals, and third and fourth ones of the plurality of nodes comprising an output; and

at least one conductor inductively coupled to the at least one thin-film element for applying a first magnetic field thereto.

2. The logic gate of claim 1 wherein the plurality of solid-state components are configured to operate as an AND gate.

3. The logic gate of claim 1 wherein the plurality of solid-state components are configured to operate as a NAND gate.

4. The logic gate of claim 1 wherein the plurality of solid-state components are configured to operate as an OR gate.

5. The logic gate of claim 1 wherein the plurality of solid-state components are configured to operate as a NOR gate.

6. The logic gate of claim 1 wherein the plurality of solid-state components are configured to operate as an XOR gate.

7. The logic gate of claim 1 wherein the plurality of solid-state components are configured to operate as a NOT gate.

8. A memory device, comprising:

a plurality of memory elements; and

selection circuitry coupled to the memory elements for communicating therewith, the selection circuitry comprising a plurality of solid-state components, each of the solid-state components comprising;

a network of thin-film elements, at least one thin-film element exhibiting giant magnetoresistance, the network having a plurality of nodes, each node representing a direct electrical connection between two of the thin-film elements, first and second ones of the plurality of nodes comprising power terminals, and third and fourth ones of the plurality of nodes comprising an output; and

at least one conductor inductively coupled to the at least one thin-film element for applying a first magnetic field thereto.

9. A method for operating a solid-state component as a logic gate, the solid-state component comprising a network of thin-film elements, at least one thin-film element exhibiting giant magnetoresistance, the network having a plurality of nodes, each node representing a direct electrical connection between two of the thin-film elements, first and second ones of the plurality of nodes comprising power terminals, and third and fourth ones of the plurality of nodes comprising an output, the solid-state component also comprising at least one conductor inductively coupled to the at least one thin-film element for applying a magnetic field thereto, the method comprising the steps of:

setting a switching threshold for the solid-state component, wherein the output of the solid-state component switches where a total field from the at least one conductor exceeds the switching threshold; and

applying an input signal to the solid-state component via the at least one conductor.

10. The method of claim 9 wherein the step of setting the switching threshold comprises adjusting the width of at least one of the plurality of conductors.

11. The method of claim 9 wherein the solid-state component comprises a plurality of conductors inductively coupled to the at least one thin-film element for applying magnetic fields thereto, and the step of setting the switching threshold comprises:

setting the amplitudes of input signals on the conductors such that the solid-state component switches only when the fields from all of the plurality of conductors are simultaneously applied; and

setting a polarity of the at least one thin-film element thereby causing the solid-state component to operate as an AND gate.

12. The method of claim 9 wherein the solid-state component comprises a plurality of conductors inductively coupled to the at least one thin-film element for applying magnetic fields thereto, and the step of setting the switching threshold comprises the steps of:

setting the amplitudes of input signals on the conductors such that the solid-state component switches only when the fields from all of the plurality of conductors are simultaneously applied; and

setting a polarity of the at least one thin-film element thereby causing the solid-state component to operate as a NAND gate.

13. The method of claim 9 wherein the solid-state component comprises a plurality of conductors inductively coupled to the at least one thin-film element for applying magnetic fields thereto, and the at least one thin-film element comprises a high-coercivity layer, the step of setting the switching threshold comprising the steps of:

setting the amplitudes of input signals on the conductors such that the field from any one of the conductors can cause the solid-state component to switch, and such that the coercivity of the high-coercivity layer cannot be exceeded by a sum of the fields from all of the conductors; and

setting a polarity of the at least one thin-film element thereby causing the solid-state component to operate as an OR gate.

14. The method of claim 9 wherein the solid-state component comprises a plurality of conductors inductively coupled to the at least one thin-film element for applying magnetic fields thereto, and the at least one thin-film element comprises a high-coercivity layer, the step of setting the switching threshold comprising the steps of:

setting the amplitudes of input signals on the conductors such that the field from any one of the conductors can cause the solid-state component to switch, and such that the coercivity of the high-coercivity layer cannot be exceeded by a sum of the fields from all of the conductors; and

setting a polarity of the at least one thin-film element thereby causing the solid-state component to operate as a NOR gate.

15. The method of claim 9 wherein the solid-state component comprises a plurality of conductors inductively coupled to the at least one thin-film element for applying magnetic fields thereto, and the at least one thin-film element comprises a high-coercivity element and a low-coercivity element, the step of setting the switching threshold comprising:

setting the amplitudes of input signals on the conductors such that the field from one of the conductors causes only the low-coercivity element to switch, and the fields from more than one of the conductors causes both the low-coercivity and high-coercivity elements to switch; and

setting a polarity of the at least one thin-film element thereby causing the solid-state component to operate as an exclusive-OR gate.

16. The method of claim 9 wherein the step of setting the switching threshold comprises configuring the solid-state component such that the output provides a signal which is an inversion of the input signal on the at least one conductor, thereby causing the solid-state component to operate as a NOT gate.

17. A method for linear operation of a solid-state component, the solid state component comprising a network of thin-film elements, at least one thin-film element exhibiting giant magnetoresistance, the network having a plurality of nodes, each node representing a direct electrical connection between two of the thin-film elements, first and second ones of the plurality of nodes comprising power terminals, and third and fourth ones of the plurality of nodes comprising an output, the solid-state component also comprising a conductor inductively coupled to the at least one thin-film element for applying a magnetic field thereto, the method comprising the step of substantially eliminating hysteresis from the at least one thin-film element exhibiting giant magnetoresistance.

18. The method of claim 17 wherein the at least one thin-film element comprises a low-coercivity element which is characterized by an easy axis and an anisotropy field, the eliminating step comprising applying a bias field perpendicular to the easy axis having a magnitude larger than the anisotropy field.

19. The method of claim 18 wherein the bias field is applied with a magnetic device external to the solid-state component.

20. The method of claim 18 wherein the bias field is applied with individually deposited magnets on the solid-state component.

21. The method of claim 18 wherein the bias field is applied by current in a stripline deposited on the solid-state component.

22. The method of claim 17 wherein the at least one thin-film element comprises a cobalt layer characterized by an easy axis and a permalloy layer characterized by a hard axis, the eliminating step comprising the steps of:

depositing the cobalt layer such that the easy axis of the cobalt layer is parallel to the hard axis of the permalloy layer; and

driving and sensing the permalloy layer along the hard axis of the permalloy layer.

23. The method of claim 22 wherein the depositing step comprises saturating the cobalt layer during the depositing step in a direction perpendicular to the easy axis of the permalloy layer.

24. The method of claim 17 wherein the at least one thin-film element comprises a plurality of permalloy layers, the eliminating step comprising:

applying an input signal to the conductor, the input signal comprising a stream of data samples; and

applying a pulse on the conductor following each data sample having sufficient amplitude to saturate the permalloy layers to an initial state.