×

Apparatus and method for defect testing of integrated circuits

  • US 6,031,386 A
  • Filed: 10/31/1997
  • Issued: 02/29/2000
  • Est. Priority Date: 10/31/1997
  • Status: Expired due to Term
First Claim
Patent Images

1. An apparatus for defect or failure-mechanism testing of an integrated circuit (IC), comprising:

  • (a) a source connected to a power supply terminal of the IC to provide an operating voltage thereto;

    (b) means connected to a plurality of input pins of the IC for providing a vector set of voltage inputs to the IC for toggling the IC between logic states thereof; and

    (c) means connected to the power supply terminal of the IC for measuring a transient voltage component (VDDT) generated in response to the toggling of the IC between logic states thereof, with the transient voltage component providing an indication of any defects or failure-mechanisms present within the IC.

View all claims
  • 2 Assignments
Timeline View
Assignment View
    ×
    ×