TTL input stage for negative supply systems
First Claim
1. A circuit comprising:
- a transistor-transistor logic (TTL) stage comprising;
a first load having a first terminal and a second terminal, said first load having a first voltage drop across said first terminal and said second terminal when a control voltage is applied to said first terminal;
a first transistor having a control terminal electrically coupled to a reference voltage, said first transistor having a first current carrying terminal and a second current carrying terminal, said first current carrying terminal of said first transistor being electrically coupled to said second terminal of said first load;
a second load electrically coupled in series between said second current carrying terminal of said first transistor and a negative voltage;
a third load having a first terminal, electrically coupled to said reference voltage, and a second terminal, said second current carrying terminal providing an output of said TTL stage; and
a second transistor having a control terminal electrically coupled to said second current carrying terminal of said first transistor, said second transistor having a first current carrying terminal electrically coupled to said second terminal of said third load and having a second current carrying terminal electrically coupled to said negative voltage.
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Accused Products
Abstract
A TTL input stage for negative supply voltage systems is described herein which obviates the need for a positive supply and a level shifter. In one embodiment, a first JFET current source, the emitter/collector of a PNP bipolar transistor, and a second JFET current source are connected in series between a control input and a negative supply voltage. The base of the bipolar transistor is connected to ground. At a control input of 2Vbe above ground, the PNP transistor has a Vbe drop across its emitter/base junction, and each of the identical JFETs has a Vbe drop across it. An NPN bipolar transistor, having its base connected to the source of the second JFET and its emitter connected to the negative voltage, is turned on by the Vbe drop across the second JFET to provide the output of the TTL input stage. In one embodiment, the TTL input stage is a control circuit for turning an output MOSFET on and off. A circuit providing hysteresis of the threshold for switching between logic levels may be included as part of the TTL input stage.
15 Citations
19 Claims
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1. A circuit comprising:
a transistor-transistor logic (TTL) stage comprising; a first load having a first terminal and a second terminal, said first load having a first voltage drop across said first terminal and said second terminal when a control voltage is applied to said first terminal; a first transistor having a control terminal electrically coupled to a reference voltage, said first transistor having a first current carrying terminal and a second current carrying terminal, said first current carrying terminal of said first transistor being electrically coupled to said second terminal of said first load; a second load electrically coupled in series between said second current carrying terminal of said first transistor and a negative voltage; a third load having a first terminal, electrically coupled to said reference voltage, and a second terminal, said second current carrying terminal providing an output of said TTL stage; and a second transistor having a control terminal electrically coupled to said second current carrying terminal of said first transistor, said second transistor having a first current carrying terminal electrically coupled to said second terminal of said third load and having a second current carrying terminal electrically coupled to said negative voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A method performed by a transistor-transistor logic (TTC) stage to decode TTL signals to generation an output signal comprising:
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applying a control voltage to a first current carrying terminal of a first load, said first load having a first voltage drop across said first current carrying terminal and a second current carrying terminal when said control voltage is applied to said first current carrying terminal; applying a reference voltage to a control terminal of a first transistor, said first transistor having a first current carrying terminal and a second current carrying terminal, said first current carrying terminal of said first transistor being electrically coupled to said second current carrying terminal of said first load; generating a second voltage drop across a second load electrically coupled in series between said second current carrying terminal of said first transistor and a negative voltage; applying said reference voltage to a first current carrying terminal of a third load, said third load also having a second current carrying terminal, said second current carrying terminal providing an output of said TTL stage; and applying a voltage at said second current carrying terminal of said first transistor to a control terminal of a second transistor, said second transistor having a first current carrying terminal electrically coupled to said second current carrying terminal of said third load and having a second current carrying terminal electrically coupled to said negative voltage. - View Dependent Claims (19)
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Specification