Low voltage CMOS circuit for on/off chip drive at high voltage

• US 6,031,394 A
• Filed: 01/08/1998
• Issued: 02/29/2000
• Est. Priority Date: 01/08/1998
• Status: Expired due to Term

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Garvin, Stacy J., Cranford, Hayden C. Jr., Stephens, Geoffrey B.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): CHO, JAMES HYONCHOL
• Application Number:
  US09/004,565
• Time in Patent Office: 782 Days
• Field of Search: 326/81, 326/80, 326/33, 326/83, 326/58, 326/86, 326/121, 326/57, 326/68
• US Class Current: 326/81
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 3/356147 using pass gates

Abstract

A low voltage CMOS circuit and method provide output current ability meeting multimode requirements of high voltage off-chip drivers while protecting the CMOS devices from various breakdown mechanisms. The circuit and method utilize intermediate voltages between two power rails and voltage division techniques to limit the voltages to acceptable limits for drain-to-source, gate-to-drain, and gate-to-source of CMOS devices in any chosen technology. The circuit comprises first and second CMOS cascode chains connected between a high voltage power rail, e.g 5 volt and a reference potential power rail, e.g. ground. Each CMOS cascode chain comprises first and second p-type MOS devices in series with first and second n-type MOS devices. An input circuit is coupled to a node at the midpoint of the first CMOS cascode chain. A bias voltage, typically 3.3 volts is connected to the NMOS devices in the first and CMOS cascode chains. A second bias voltage is coupled to the PMOS devices in the first and second CMOS cascode chains. An output is provided from the second CMOS cascode chain to a third CMOS cascode chain for purposes of providing sufficient pullup capability to drive an output circuit comprising a fourth CMOS cascode chain between the high and reference potentials without exceeding the breakdown mechanisms for any MOS device in the CMOS cascode chains.

Claims

1. A low voltage and low current CMOS circuit for providing a high voltage output while protecting the CMOS devices from various breakdown mechanisms, comprising:

a) a first CMOS cascode chain including PMOS and NMOS devices;

b) a second CMOS cascode chain including PMOS and NMOS devices and connected in cascade with the first CMOS cascode chain;

c) means cross coupling the PMOS devices in the first and second cascode chains;

d) means cross coupling the NMOS devices in the first and second cascode chains;

e) a third CMOS cascode chain including PMOS and NMOS devices, the PMOS devices coupled to the cross coupled PMOS and the NMOS devices coupled to the cross coupled NMOS devices for buffering the PMOS devices in the first and second cascode chains;

f) high and low voltage power rails connected to the first, second and third CMOS cascode chains;

g) an input circuit connected to the first and second CMOS cascode chains and providing low voltage input signal levels;

h) means coupling the gates of the first, second and third CMOS cascode chains to bias supplies for limiting current flow in the first, second and third cascode chains

i) a CMOS cascode output circuit including PMOS and NMOS devices and connected between the high and low voltage power rails and to the third CMOS cascode chain, the output circuit providing a high voltage or low voltage output according to the input signal level;

j) a clamping circuit connected to the PMOS output devices for limiting the maximum voltage across the PMOS output devices; and

k) means dynamically changing the bias levels of the PMOS and NMOS devices in the first, second, third cascode chains and the output circuit whereby such PMOS and NMOS devices do not exceed their breakdown voltages as the output circuit provides a high or low voltage output.

2. The circuit of claim 1 further comprising:

a) a first bias supply connected to the NMOS devices in the first and second CMOS cascode chains whereby the voltage across the NMOS devices does not exceed a breakdown voltage for said NMOS devices as the input signal level changes.

3. The circuit of claim 1 further comprising:

a) a second bias supply connected to the PMOS devices in the first and second CMOS chains whereby the voltage across the PMOS devices does not exceed a breakdown voltage for said PMOS devices as the input signal level changes.

4. The circuit of claim 1 further comprising:

a) a third CMOS cascode chain and connected to the first and second CMOS cascode chains for providing pull-up capabilities to the CMOS cascode output circuit.

5. The circuit of claim 1 further comprising:

a) an inverter connected to the input circuit and the CMOS cascode output circuit.

6. The circuit of claim 1 further comprising:

a) first and second inverters in cascade connected to the second CMOS cascode circuit and the CMOS cascode output circuit.

7. The circuit of claim 1 further comprising:

a) first and second inverters connected to the first CMOS cascade circuit and to the CMOS cascode output circuit.

8. The circuit of claim 1 further comprising:

a) means connected to the output of the second CMOS cascode circuit and providing a reference potential between the output high and low voltage levels.

9. The circuit of claim 1 wherein each CMOS cascode comprises:

a) a PMOS cascode circuit in series with an NMOS cascode circuit.

10. The circuit of claim 9 further comprising:

a) a first bias supply connected to the NMOS devices in the first and second CMOS cascode chains whereby the voltage across the NMOS devices does not exceed a breakdown voltage for said NMOS devices as the input signal level changes.

11. The circuit of claim 9 further comprising:

a) a second bias supply connected to the PMOS devices in the first and second CMOS chains whereby the voltage across the PMOS devices does not exceed a breakdown voltage for said PMOS devices as the input signal level changes.

12. The circuit of claim 9 wherein the input circuit is connected to the midpoint between the PMOS and NMOS devices in the first CMOS cascode chain.

13. The circuit of claim 9 further comprising:

a) an output terminal connected to the midpoint between the PMOS and NMOS devices in the CMOS cascode output circuit.

14. The circuit of claim 1 further comprising:

a) a load resistor connected between the high voltage power rail and CMOS cascode output circuit.

15. The circuit of claim 9 wherein the PMOS devices of the first and second CMOS cascode chains are cross-coupled as a pullup device.

16. A low voltage CMOS circuit for providing a current output that picks a relay to allow a token ring device to insert into a ring according to the IEEE 802.5 specification while protecting the CMOS devices from various breakdown mechanisms, comprising:

a) a first CMOS cascode chain including PMOS and NMOS devices;

b) a second CMOS cascode chain including PMOS and NMOS devices and connected in cascade with the first CMOS device cascode chain;

c) means connected to the second cascode circuit for generating a bias supply within the CMOS circuit;

d) high and low voltage power rails connected to the first and second cascode chains;

e) an input circuit connected to the first CMOS cascode chain for receiving a token ring device;

f) a CMOS cascode output circuit including PMOS and NMOS devices and connected between the high and low voltage power rails;

g) a clamping device connected to the output circuit to limit the maximum drain source voltage of the PMOS devices;

h) means connecting the second cascode chain to the PMOS devices in the output circuit as a P switch; and

i) means connecting the input circuit to the NMOS devices in the output circuit as an N switch whereby when a token ring device is inserted into the input circuit the output circuit will operate at voltage and current levels satisfying the IEEE 802.5 specification without breakdown of the PMOS and NMOS devices and when the token ring device is removed from the input circuit, the output circuit will operate at different voltage and current levels satisfying the IEEE 902.5 specification without breakdown of the PMOS and NMOS devices.