Controlled gain amplifier with variable control exponent

• US 6,031,421 A
• Filed: 07/22/1998
• Issued: 02/29/2000
• Est. Priority Date: 07/22/1998
• Status: Expired due to Term

• Current Assignee: Mcewan Technologies LLC
• Original Assignee: Thomas E. Mcewan
• Inventors: McEwan, Thomas E.
• Primary Examiner(s): Lee, Benny
• Assistant Examiner(s): Choe, Henry
• Application Number:
  US09/120,991
• Time in Patent Office: 587 Days
• Field of Search: 330/90, 330/137, 330/251, 330/51, 330/207 A, 327/124, 327/172, 327/173, 327/174, 327/175, 327/176
• US Class Current: 330/10
• CPC Class Codes: G01S 7/34 Gain of receiver varied automatically during pulse-recurrence period, e.g. anti-clutter gain control
• CPC Class Codes: H03G 1/0088 using discontinuously variable devices, e.g. switch-operated
• CPC Class Codes: H04N 5/52 Automatic gain control

Abstract

A controlled-gain amplifier has a gain control port responsive to a control voltage Vc, and produces a gain proportional to Vc raised to a fixed or continuously variable power X, such that gain=K(Vc)^X, where K is a constant. Precise gain control is achieved through the use of pulse width modulation (PWM) control of cascaded amplifier stages. A PWM regulator linearly controls the gain of each amplifier stage, and multiple stages are cascaded for (Vc)^N gain control, where N is an integer. One or more amplifier stages may contain a variable low pass filter that allows continuous control of the control exponent to produce non-integer exponents. The circuit can be used as a Sensitivity-Time-Control (STC) circuit in sampling-type radar systems, or in ultrasonic rangefinders, where the gain of the receiver needs to increase exponentially with increasing range.

Claims

1. A controlled-gain amplifier comprising:

a pulse width modulation (PWM) regulator responsive to an error signal produced by comparing a gain control voltage V_c to a PWM feedback voltage V_ave to produce a clock signal having a duty cycle determined by the applied control voltage V_c ;

At least one switched amplifier stage, each stage being connected to the clock signal from the PWM regulator and having a gain proportional to the duty cycle of the clock signal.

2. The amplifier of claim 1 wherein each amplifier stage comprises:

a switch having an input terminal and toggled by the PWM regulator clock signal;

a lowpass filter connected to an output terminal of the switch;

a fixed gain amplifier having an input connected to the lowpass filter.

3. The amplifier of claim 2 wherein the lowpass filter has an adjustable cutoff frequency.

4. The amplifier of claim 1 wherein the gain of each amplifier stage is linearly proportional to the control voltage.

5. The amplifier of claim 1 comprising more than one amplifier stage, wherein the cascaded gain is proportional to the control voltage raised to a control exponent.

6. The amplifier of claim 2 wherein the PWM regulator comprises a PWM switch toggled by the clock signal from the PWM regulator.

7. The amplifier of claim 6 wherein each switch in the one or more amplifier stages and the PWM switch are all toggled together.

8. The amplifier of claim 6 wherein the PWM switch has an input terminal connected to a DC reference, and further comprising a PWM low pass filter connected to an output terminal of the PWM switch, a PWM control amplifier having a first input connected to the output of the PWM lowpass filter and a second input connected to the control voltage.

9. The amplifier of claim 8 further comprising a PWM modulator having an input connected to the output of the PWM control amplifier to vary the duty cycle of an input clock signal to equalize the output of the PWM lowpass filter with the control voltage.

10. The amplifier of claim 1 wherein the control voltage is a voltage ramp.

11. The amplifier of claim 1 wherein the PWM clock signal has a frequency substantially higher than the frequency of an input signal to the first amplifier stage.

12. In a sampling radar or ultrasonic rangefinder, a sensitivity-time-control (STC) circuit comprising an amplifier of claim 1.

13. A controlled-gain amplifier comprising:

a pulse width modulation (PWM) regulator having a variable duty cycle clock output the PWM regulator being responsive to an error signal produced by comparing a gain control voltage Vc to a PWM feedback voltage Vave to produce the variable duty cycle clock output;

a first switch toggled in proportion to the variable duty cycle clock output of the PWM regulator and having one terminal connected to a signal input,

a first lowpass filter having first and second terminals with the first terminal connected to a second terminal of the first switch,

a first fixed-gain amplifier having an input connected to the second terminal of the first lowpass filter.

14. The amplifier of claim 13 further including a second switch, second lowpass filter and second fixed-gain amplifier cascaded with the first switch, first lowpass filter, and first fixed-gain amplifier.

15. The amplifier of claim 14 where at least one of the lowpass filters has a continuously adjustable cutoff to vary a control exponent.

16. The amplifier of claim 13 where the first switch has a third terminal connected to ground such that the second terminal of the switch switches between the first and third terminals at the clock frequency and in proportion to the clock duty cycle.

17. A method of amplifying an input signal with a controlled gain comprising:

generating a variable duty cycle clock signal with a duty cycle determined by a control voltage by comparing the control voltage to a feedback voltage;

chopping the input signal in proportion to the duty cycle of the clock signal;

averaging the chopped signal to produce an attenuated version of the input signal;

amplifying the attenuated version of the input signal to produce an amplified signal having a gain proportional to the control voltage.

18. The method of claim 17 further comprising performing the steps of chopping, averaging, and amplifying in successive cascaded stages to produce an output signal having a gain proportional to the control voltage raised to a control exponent.

19. The method of claim 17 wherein the step of averaging the chopped signal is performed by passing the chopped signal through a lowpass filter, and further comprising adjusting the cutoff frequency of the lowpass filter to produce a gain proportional to the control voltage raised to a non-integer exponent.