Controlled gain amplifier with variable control exponent
First Claim
1. A controlled-gain amplifier comprising:
- a pulse width modulation (PWM) regulator responsive to an error signal produced by comparing a gain control voltage Vc to a PWM feedback voltage Vave to produce a clock signal having a duty cycle determined by the applied control voltage Vc ;
At least one switched amplifier stage, each stage being connected to the clock signal from the PWM regulator and having a gain proportional to the duty cycle of the clock signal.
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Accused Products
Abstract
A controlled-gain amplifier has a gain control port responsive to a control voltage Vc, and produces a gain proportional to Vc raised to a fixed or continuously variable power X, such that gain=K(Vc)X, where K is a constant. Precise gain control is achieved through the use of pulse width modulation (PWM) control of cascaded amplifier stages. A PWM regulator linearly controls the gain of each amplifier stage, and multiple stages are cascaded for (Vc)N gain control, where N is an integer. One or more amplifier stages may contain a variable low pass filter that allows continuous control of the control exponent to produce non-integer exponents. The circuit can be used as a Sensitivity-Time-Control (STC) circuit in sampling-type radar systems, or in ultrasonic rangefinders, where the gain of the receiver needs to increase exponentially with increasing range.
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Citations
19 Claims
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1. A controlled-gain amplifier comprising:
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a pulse width modulation (PWM) regulator responsive to an error signal produced by comparing a gain control voltage Vc to a PWM feedback voltage Vave to produce a clock signal having a duty cycle determined by the applied control voltage Vc ; At least one switched amplifier stage, each stage being connected to the clock signal from the PWM regulator and having a gain proportional to the duty cycle of the clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A controlled-gain amplifier comprising:
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a pulse width modulation (PWM) regulator having a variable duty cycle clock output the PWM regulator being responsive to an error signal produced by comparing a gain control voltage Vc to a PWM feedback voltage Vave to produce the variable duty cycle clock output; a first switch toggled in proportion to the variable duty cycle clock output of the PWM regulator and having one terminal connected to a signal input, a first lowpass filter having first and second terminals with the first terminal connected to a second terminal of the first switch, a first fixed-gain amplifier having an input connected to the second terminal of the first lowpass filter. - View Dependent Claims (14, 15, 16)
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17. A method of amplifying an input signal with a controlled gain comprising:
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generating a variable duty cycle clock signal with a duty cycle determined by a control voltage by comparing the control voltage to a feedback voltage; chopping the input signal in proportion to the duty cycle of the clock signal; averaging the chopped signal to produce an attenuated version of the input signal; amplifying the attenuated version of the input signal to produce an amplified signal having a gain proportional to the control voltage. - View Dependent Claims (18, 19)
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Specification