DC bus voltage balancing and control in multilevel inverters

• US 6,031,738 A
• Filed: 06/16/1998
• Issued: 02/29/2000
• Est. Priority Date: 06/16/1998
• Status: Expired due to Term

• Current Assignee: Wisconsin Alumni Research Foundation (University of Wisconsin System)
• Original Assignee: Wisconsin Alumni Research Foundation (University of Wisconsin System)
• Inventors: Lipo, Thomas A., Sinha, Gautam
• Primary Examiner(s): STERRETT, JEFFREY L
• Application Number:
  US09/098,118
• Time in Patent Office: 623 Days
• Field of Search: 363/34, 363/37, 363/43, 363/95, 363/98, 363/132
• US Class Current: 363/37
• CPC Class Codes: H02M 7/487 Neutral point clamped inverters
• CPC Class Codes: H02M 7/5395 by pulse-width modulation
• CPC Class Codes: H02P 27/14 with three or more levels of voltage

Abstract

A multilevel inverter system having four or more levels of output voltage on each inverter output line. The voltage across each of three or more series connected DC bus capacitors is provided to an inverter which is formed to have redundant switching states, such as a plurality of controlled switching devices and diodes connected in a diode-clamped multilevel inverter configuration. The switching of the switching devices is controlled to provide a selected output voltage waveform utilizing redundant switching states, when such states are available on each voltage transition, by selecting a one of the available switching states that serves to provide the desired phase-to-phase voltages and to tend to equalize the voltages across the DC bus capacitors. Active or passive rectifiers may be used to provide the DC voltage across the DC bus lines and across the DC bus capacitors. Separate rectifiers may be provided for each capacitor which are supplied from secondaries of transformers connected to the three phase input lines to provide isolation and voltage level adjustment. The multilevel inverter system provides output voltage waveforms with lower total harmonic distortion that conventional two or three level inverters, while maintaining voltage balance across the several DC bus capacitors.

Claims

1. A multilevel inverter system comprising:

(a) three DC bus capacitors connected in series at nodes between the capacitors and with the series connected capacitors connected across DC bus lines;

(b) an inverter connected to the DC bus lines and to the nodes between the capacitors to be supplied with the voltages therefrom, the inverter comprised of a plurality of controlled switching devices connected in a configuration to provide three-phase power on three output lines and at four voltage levels on each output line;

(c) control means connected to the switching devices of the inverter to control the switching of the same;

the control means controlling the switching of the switching devices to provide a selected output voltage waveform at the output lines; and

(d) a transformer having a three-phase primary coupled to three separate single-phase secondaries, the primary connected to receive three-phase power at AC input lines, and a single-phase bridge rectifier connected to each secondary to provide the rectified power therefrom across one of the DC bus capacitors.

2. A multilevel inverter system comprising:

(a) three DC bus capacitors connected in series at nodes between the capacitors and with the series connected capacitors connected across high and low DC bus lines;

(b) an inverter connected to the high and low DC bus lines and to DC bus lines connected to the nodes between the capacitors to be supplied with the voltages therefrom, the inverter comprised of a plurality of controlled switching devices connected in a configuration having redundant switching states to provide three-phase power on three output load lines and at four voltage levels on each output line; and

(c) control means receiving signals indicative of the voltages across the DC bus capacitors and load currents on the output lines and connected to the switching devices of the inverter to control the switching of the same, the control means using the signals indicative of the voltages and currents at each switching event for controlling the switching of the switching devices to provide a selected output voltage waveform at the output lines utilizing redundant switching states when such states are available to select one of the available redundant switching states that serves to provide the desired phase-to-phase voltages and to tend to equalize the voltages across the DC bus capacitors, wherein the control means determines which switching state to utilize of the available switching states by evaluating the quantity Q=Δ

V_C1 I₁ +Δ

V_C2 I₂ +Δ

V_C3 I₃ for each available switching state and selecting one of the available redundant switching states for which the quantity Q is ≧

0, wherein Δ

V_C1, Δ

V_C2, and Δ

V_C3 are the respective differences between the measured voltage across each capacitor and the nominal voltage across each capacitor, and I₁, I₂, and I₃ are currents flowing through DC bus lines to the inverter determined for the load currents and the available switching states.

3. The inverter system of claim 2 wherein the control means controls the inverter to switch the switching devices to provide a pulse-width modulated waveform of the voltage on the phase output lines.

4. The inverter system of claim 2 wherein there are three DC bus capacitors connected in series, two outer capacitors and one inner capacitor, and wherein at modulation depths at which sufficient redundant states are not available to effectively equalize all of the capacitor voltages, the control means controls the switching devices utilizing one of the available redundant states that transfers charge from the outer capacitors to the inner capacitor.

5. The inverter system of claim 2 wherein the inverter comprises the controlled switching devices and a plurality of diodes connected in a diode clamped multilevel inverter configuration.

6. The inverter system of claim 2 wherein the control means controls the switching devices to switch under sine-triangle pulse-width modulation for modulation depths m_a less than a selected value and under space vector modulation for modulation depths m_a greater than the selected value where ##EQU11## and V_ph, pk is the load phase peak voltage and V_DC is the voltage across the high and low DC bus lines.

7. The inverter system of claim 6 wherein the selected value of m_a is about 0.7.

8. The inverter system of claim 2 further including a rectifier connected to the high and low DC bus lines and having AC input lines to convert AC input power at the input lines to a DC voltage at the DC bus lines.

9. The inverter system of claim 8 wherein the rectifier further is connected to the nodes between the DC bus capacitors to provide intermediate DC voltages across each capacitor.

10. The inverter system of claim 9 wherein the rectifier includes a plurality of controlled switching devices and diodes and wherein the control means is connected to the controlled switching devices to control the same, the switching devices and diodes connected in the rectifier in a diode-clamped rectifier configuration and wherein the control means provides control signals to the switching devices to switch the switching devices to provide selected DC voltages across the DC bus capacitors.

11. The inverter system of claim 10 wherein the rectifier switching devices are switched in accordance with a hysteresis current control scheme to generate substantially unity displacement power factor input currents at the AC input lines.

12. The inverter system of claim 9 further including a transformer having a three-phase primary coupled to three separate single-phase secondaries, the primary connected to receive the three-phase power at the AC input lines, wherein the rectifier comprises a single-phase bridge rectifier connected to each secondary to provide the rectified power therefrom across one of the DC bus capacitors.

13. The inverter system of claim 9 further including plural three-phase transformers, each having primaries connected to receive AC power at the AC input lines and each having three-phase secondaries, and a three-phase rectifier connected to the secondary of each transformer and connected to provide a DC voltage across one of the DC bus capacitors.

14. A method of balancing the voltages on the DC bus capacitors connected to a multilevel inverter that provides multilevel three-phase power on output lines, wherein at least three DC bus capacitors are connected in series at nodes between the capacitors with the three series capacitors connected across high and low DC bus lines, the inverter connected to the high and low DC bus lines and to intermediate bus lines connected to the nodes between the capacitors to be supplied with the voltages therefrom and wherein the inverter is comprised of a plurality of controlled switching devices and diodes connected in a configuration having redundant switching states to provide three phase power on three output lines and at at least four voltage levels on each output line, comprising the steps of:

(a) monitoring signals indicative of the voltages across the DC bus capacitors and the load currents on the output lines; and

(b) switching the switching devices of the inverter to provide a desired output voltage waveform at the inverter output lines utilizing redundant switching states when such states are available on each voltage transition by using the signals indicative of the voltages and currents to select one of the available redundant switching states that serves to provide the desired phase-to-phase voltages and to tend to equalize the voltages across the DC bus capacitors, wherein there are at least two outer DC bus capacitors and an inner DC bus capacitor, and wherein at modulation depths at which sufficient redundant states are not available to effectively equalize all of the capacitor voltages, the switching devices are switched utilizing one of the available redundant states that transfers charge from the outer capacitors to the inner capacitor.

15. A multilevel inverter system comprising:

(a) three DC bus capacitors connected in series at nodes between the capacitors and with the series connected capacitors connected across high and low DC bus lines;

(b) an inverter connected to the high and low DC bus lines and to DC bus lines connected to the nodes between the capacitors to be supplied with the voltages therefrom, the inverter comprised of a plurality of controlled switching devices connected in a configuration having redundant switching states to provide three-phase power on three output load lines and at four voltage levels on each output line; and

(c) control means receiving signals indicative of the voltages across the DC bus capacitors and load currents on the output lines and connected to the switching devices of the inverter to control the switching of the same, the control means using the signals indicative of the voltages and currents at each switching event for controlling the switching of the switching devices to provide a selected output voltage waveform at the output lines utilizing redundant switching states when such states are available to select one of the available redundant switching states that serves to provide the desired phase-to-phase voltages and to tend to equalize the voltages across the DC bus capacitors, wherein the control means determines which switching state to utilize of the available switching states by evaluating the quantity Q=max {Δ

V_c1 i_c1, Δ

V_c2 i_c2, Δ

V_c3 i_c3 } for each available switching state and selecting one of the available redundant switching states for which the quantity Q is ≦

0, wherein Δ

V_c1, Δ

V_c2, and Δ

V_c3 are the respective differences between the measured voltage across each capacitor and the nominal voltage across each capacitor, and i_c1, i_c2, and i_c3 are the currents flowing through the respective capacitors determined for the load currents and the available switching states.

16. The inverter system of claim 15 wherein the control means selects the one of the available redundant switching states for which the quantity Q is most negative.

17. A multilevel inverter system comprising:

(a) at least three DC bus capacitors connected in series at nodes between the capacitors and with the series connected capacitors connected across high and low DC bus lines;

(b) an inverter connected to the high and low DC bus lines and to DC bus lines connected to the nodes between the capacitors to be supplied with the voltages therefrom, the inverter comprised of a plurality of controlled switching devices connected in a configuration having redundant switching states to provide three-phase power on three output load lines and at least four voltage levels on each output line; and

(c) control means receiving signals indicative of the voltages across the DC bus capacitors and load currents on the output lines and connected to the switching devices of the inverter to control the switching of the same, the control means using the signals indicative of the voltages and currents at each switching event for controlling the switching of the switching devices to provide a selected output voltage waveform at the output lines utilizing redundant switching states when such states are available to select one of the available redundant switching states that serves to provide the desired phase-to-phase voltages and to tend to equalize the voltages across the DC bus capacitors, wherein the control means controls the inverter to switch the switching devices under sine-triangle pulse-width modulation when redundant states are available and to switch the switching devices in accordance with space vector modulation when redundant switching states are not available.

18. The inverter system of claim 17 wherein the space vector modulation is four level space vector modulation.

20. The inverter system of claim 17 wherein the selected value of m_a is about 0.7.

19. A multilevel inverter system comprising:

(a) at least three DC bus capacitors connected in series at nodes between the capacitors and with the series connected capacitors connected across high and low DC bus lines;

(b) an inverter connected to the high and low DC bus lines and to DC bus lines connected to the nodes a between the capacitors to be supplied with the voltages therefrom, the inverter comprised of a plurality of controlled switching devices and diodes connected in a diode clamped multilevel inverter configuration to provide three-phase power on three output lines and at at least four voltage levels on each output line; and

(c) control means connected to the switching devices of the inverter for controlling the switching of the switching devices to provide a selected output voltage waveform at the output lines, wherein the control means controls the switching devices to switch under pulse-width modulation for modulation depths m_a less than a selected value and under space vector modulation for modulation depths m_a greater than the selected value where ##EQU12## and V_ph, pk is the load phase peak voltage and V_DC is the voltage across the high and low DC bus lines.

21. The inverter system of claim 19 wherein the pulse width modulation is sine-triangle pulse-width modulation and the space vector modulation is four level space vector modulation.

22. A method of balancing the voltages on the DC bus capacitors connected to a multilevel inverter that provides multilevel three-phase power on output lines, wherein at least three DC bus capacitors are connected in series at nodes between the capacitors with the three series capacitors connected across high and low DC bus lines, the inverter connected to the high and low DC bus lines and to intermediate bus lines connected to the nodes between the capacitors to be supplied with the voltages therefrom and wherein the inverter is comprised of a plurality of controlled switching devices and diodes connected in a configuration having redundant switching states to provide three phase power on three output lines and at least four voltage levels on each output line, comprising the steps of:

(a) monitoring signals indicative of the voltages across the DC bus capacitors and the load currents on the output lines; and

(b) switching the switching devices of the inverter to provide a desired output voltage waveform at the inverter output lines utilizing redundant switching states when such states are available on each voltage transition by using the signals indicative of the voltages and currents to select one of the available redundant switching states that serves to provide the desired phase-to-phase voltages and to tend to equalize the voltages across the DC bus capacitors, wherein the switching devices are switched under sine-triangle pulse-width modulation when redundant states are available and switched in accordance with space vector modulation when redundant switching states are not available.

23. The method of claim 22 wherein the space vector modulation is four level space vector modulation.

24. A method of controlling an n level inverter system of the type having (n-1) DC bus capacitors connected in series across high and low DC bus lines, wherein n is at least four, and an inverter connected to the high and low DC bus lines and to DC bus lines connected to the nodes between the capacitors, the inverter comprised of controlled switching devices and diodes connected in a diode-clamped multilevel inverter configuration to provide three-phase power on three output lines at n voltage levels on each output line, comprising the steps of:

(a) monitoring signals indicative of the voltages across the DC bus capacitors and the load currents on the output lines; and

(b) controlling the switching of the switching devices to provide a selected output voltage waveform at the output lines using redundant switching states when such states are available on each voltage transition, and determining which state to utilize by evaluating the quantity Q=max {Δ

V_c, i_c, Δ

V_c2 i_c2, . . . , Δ

V_c(n-1) i_c(n-1) } for each available switching state and selecting one of the available redundant switching states for which the quantity Q is ≦

0, wherein Δ

V_c1, Δ

V_c2, . . . , Δ

V_c(n-1) are the respective differences between the measured voltage across each capacitor and the nominal voltage across each capacitor, and i_C1, i_C2, . . . , i_C(n-1) are the currents flowing through the respective capacitors for the load currents and the available switching states.

25. The method of claim 24 wherein the one of the available switching states is selected for which Q is most negative.

26. The method of claim 24 wherein n is four.

27. A method of balancing the voltages on the DC bus capacitors connected to a multilevel inverter that provides multilevel three-phase power on output lines, wherein three DC bus capacitors are connected in series at nodes between the capacitors with the three series capacitors connected across high and low DC bus lines, the inverter connected to the high and low DC bus lines and to intermediate bus lines connected to the nodes between the capacitors to be supplied with the voltages therefrom and wherein the inverter is comprised of a plurality of controlled switching devices and diodes connected in a configuration having redundant switching states to provide three phase power on three output lines and at four voltage levels on each output line, comprising the steps of:

(a) monitoring signals indicative of the voltages across the DC bus capacitors and the load currents on the output lines; and

(b) switching the switching devices of the inverter to provide a desired output voltage waveform at the inverter output lines utilizing redundant switching states when such states are available on each voltage transition by using the signals indicative of the voltages and currents to select one of the available redundant switching states that serves to provide the desired phase-to-phase voltages and to tend to equalize the voltages across the DC bus capacitors, wherein the switching state to be utilized of the available switching states is determined by evaluating the quantity Q=Δ

V_C1 I₁ +Δ

V_C2 I₂ +Δ

V_C3 I₃ for each available switching state and selecting one of the available redundant switching states for which the quantity Q is ≧

0, wherein Δ

V_C1, Δ

V_C2, and Δ

V_C3 are the respective differences between the measured voltage across each capacitor and the nominal voltage across each capacitor, and I₁, I₂, and I₃ are currents flowing through the DC bus lines to the inverter determined for the load currents and the available switching states.

28. The method of claim 27 wherein the switching devices are switched to provide a pulse-width modulated waveform of the voltage on the phase lines.

29. The method of claim 27 wherein the inverter has the switching devices and a plurality of diodes connected in a diode clamped multilevel inverter configuration.

30. The method of claim 27 wherein the switching devices are switched under sine-triangle pulse-width modulation for modulation depths m_a less than a selected value and under space vector modulation for modulation depths m_a greater than the selected value, where ##EQU13## and V_ph, pk is the load phase peak voltage and V_DC is the voltage across the high and low DC bus lines.

31. A multilevel invert system comprising:

(a) n-1 DC bus capacitors connected in series at nodes between the capacitors and with the series connected capacitors connected across high and low DC bus lines wherein n is a selected number of output voltage levels for the inverter and is at least four;

(b) an inverter connected to the high and low DC bus lines and to DC bus lines connected to the nodes between the capacitors to be supplied with the voltages therefrom, the inverter comprised of a plurality of controlled switching devices and diodes connected in a diode clamped multilevel inverter configuration to provide three-phase power on three output lines and at n voltage levels on each output line; and

(c) control means receiving signals indicative of the voltages across the DC bus capacitors and load currents on the output lines and connected to the switching devices of the inverter to control the switching of the same, the control means using the signals indicative of the voltages and currents at each switching event for controlling the switching of the switching devices to provide a selected output voltage waveform at the output lines utilizing redundant switching states when such states are available to select one of the available redundant switching states that serves to provide the desired phase-to-phase voltages and to tend to equalize the voltages across the DC bus capacitors, wherein the control means determines which switching state to utilize of the available switching states by evaluating the quantity Q=max {Δ

V_c1 i_c1, Δ

V_c2,i_c2, . . . , Δ

V_c(n-1) i_c(n-1) } for each available switching state and selecting one of the available redundant switching states for which the quantity Q is ≦

0, wherein Δ

V_c1, Δ

V_c2, . . . , Δ

V_c(n-1) are the respective differences between the measured voltage across each capacitor and the nominal voltage across each capacitor, and i_c1, i_c2, . . . , i_c(n-1) are the currents flowing through the respective capacitors determined for the load currents and the available switching states.

32. The inverter system of claim 31 wherein the control means controls the switching devices to switch under sine-triangle pulse-width modulation for modulation depths ma less than a selected value and under space vector modulation for modulation depths ma greater than the selected value.

33. The inverter system of claim 31 wherein n is equal to four.

34. The inverter system of claim 31 wherein the control means selects the one of the available redundant switching states for which the quantity Q is most negative.