Combining hardware and software to provide an improved microprocessor
First Claim
1. A microprocessor comprising the combination of translation software, andhost hardware,the translation software running directly on the host hardware,the translation software responding to target instructions by generating instructions to run on the host hardware.
8 Assignments
0 Petitions
Accused Products
Abstract
A microprocessor for a host computer designed to execute target application programs for a target computer having a target instruction set including the combination of code morphing software, and morph host processing hardware designed to execute instructions of a host instruction set, the combination of the code morphing software and the morph host processing hardware comprising means to translate a set of target instructions into instructions of a host instruction set, means to optimize the instructions of the host instruction set translated from the target application program speculating upon the occurrence of a condition, means to determine under control of the code morphing software official state of the target computer which existed at the beginning of a translation of a set of target instructions during execution of the target application program by the microprocessor, means for updating state of the target computer from state of the host computer when a set of host instructions executes in accordance with the speculation, means to detect failure of the condition during the execution of the set of host instructions, means for updating state of the host computer from state of the target computer when a set of host instructions fails to execute in accordance with the speculation, and means to translate a new set of host instructions without the speculation when a set of host instructions fails to execute in accordance with the speculation.
263 Citations
28 Claims
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1. A microprocessor comprising the combination of translation software, and
host hardware, the translation software running directly on the host hardware, the translation software responding to target instructions by generating instructions to run on the host hardware.
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4. A microprocessor comprising the combination of translation software, and
host hardware, in which the translation software is code morphing software and the host hardware is morph host hardware, in which the code morphing software comprises: -
processes to translate target instructions of a program written for a processor having a first instruction set into primitive instructions capable of execution on the enhanced morph host hardware, and processes to store the host primitive instructions as host translations in a translation buffer from which they may be recalled and executed by the morph host hardware any number of times. - View Dependent Claims (5)
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6. A microprocessor comprising the combination of translation software,
in which the translation software is code morphing software, and host hardware, in which the host hardware is morph host hardware, and in which the enhanced morph host hardware comprises: -
a store buffer for data being transferred to memory, the store buffer including; means responding to execution of a host translation without an exception to commit data stored in the store buffer to memory, and means responding to generation of an exception or error during execution of a host translation to dump data in the store buffer without committing it to memory; an execution unit comprising; a set of working registers in the execution unit larger than a set of registers required by a target processor in a target processor execution unit; a set of target registers for holding official register state of a target processor developed in processing a target program; and in which the code morphing software comprises; means responding to execution of a host translation without an exception or error during execution of a host translation for transferring state from the sets of working registers to the target registers, and means responding to generation of an exception or error during execution of a host translation for transferring state from the sets of target registers to the sets of working registers. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13)
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14. A microprocessor for a host computer designed to execute target application programs for a target computer having a target instruction set comprising the combination of:
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code morphing software, and morph host processing hardware designed to execute instructions of a host instruction set, the combination of the code morphing software and the morph host processing hardware comprising; means to translate a set of target instructions into instructions of a host instruction set speculating upon the occurrence of a condition, means to determine under control of the code morphing software official state of the target computer which existed at the beginning of a translation of a set of target instructions during execution of the target program by the microprocessor, means for updating state of the target computer from state of the host computer when a set of host instructions executes in accordance with the speculation, means to detect failure of the condition during the execution of the set of host instructions, means for updating state of the host computer from state of the target computer when a set of host instructions fails to execute in accordance with the speculation, and means to translate a new set of host instructions without the speculation when a set of host instructions fails to execute in accordance with the speculation. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A method of executing target programs designed to be executed by a target computer having a target instruction set on a host computer having a host processor capable of executing instructions from a host instruction set different than the target instruction set, the method comprising:
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storing state of the target computer as it exists at the beginning of translating a target instruction; translating target instructions commanding an operation into a set of host instructions for executing on the host processor the operation commanded by the target instruction; storing the host instructions as a host translation in a translation buffer; executing the host translation on the host processor; updating state stored for the target computer from state of the host computer when the execution of a host translation does not generate an exception or error; and updating state of the host computer from stored state of the target computer when the execution of the host translation generates an exception or error. - View Dependent Claims (26, 27, 28)
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Specification