Method and arrangement for data transmission between units on a bus system selectively transmitting data in one of a first and a second data transmission configurations
First Claim
1. A method of operating a bus system, wherein the bus system has at least one primary unit, at least one secondary unit, at least one bus control unit, and a bus between the at least one primary unit and the at least one secondary unit, the bus having at least one address bus, at least one data bus and at least one control line, the method which comprises:
- defining a first data transmission configuration between the at least one primary unit and the at least one secondary unit, splitting a data transmission into a request data transfer and a response data transfer in the first data transmission configuration, and clearing the bus for data transmissions of other primary units and secondary units in a time between the request data transfer and the response data transfer;
defining a second data transmission configuration between the at least one primary unit and the at least one secondary unit, blocking the bus between the request data transfer and the response data transfer in the second data transmission configuration; and
controlling a data transmission between the at least one primary unit and the at least one secondary unit, addressed by the at least one primary unit, by selectively transmitting data in the first and second data transmission configurations.
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Abstract
The invention relates to a method and an arrangement for operating a bus system having at least one master unit and at least one slave unit, having a bus and a bus control unit for the bus arbitration and for controlling the data transfer. The data transmission is split into a request data transfer and a response data transfer, and, in the time between the request data transfer and the response data transfer, the bus is cleared for the data transmissions of other master units in a first data transmission configuration, or the bus is blocked between the request data transfer and the response data transfer, in a second data transmission configuration and slave units. In the case of a response transfer, the master and slave are changed round.
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Citations
29 Claims
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1. A method of operating a bus system, wherein the bus system has at least one primary unit, at least one secondary unit, at least one bus control unit, and a bus between the at least one primary unit and the at least one secondary unit, the bus having at least one address bus, at least one data bus and at least one control line, the method which comprises:
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defining a first data transmission configuration between the at least one primary unit and the at least one secondary unit, splitting a data transmission into a request data transfer and a response data transfer in the first data transmission configuration, and clearing the bus for data transmissions of other primary units and secondary units in a time between the request data transfer and the response data transfer; defining a second data transmission configuration between the at least one primary unit and the at least one secondary unit, blocking the bus between the request data transfer and the response data transfer in the second data transmission configuration; and
controlling a data transmission between the at least one primary unit and the at least one secondary unit, addressed by the at least one primary unit, by selectively transmitting data in the first and second data transmission configurations. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A circuit arrangement for operating a bus system, comprising:
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at least one primary unit; at least one secondary unit; a bus between said at least one primary unit and said at least one secondary unit having at least one address bus, at least one data bus and at least one control line; at least one bus control unit controlling said bus and controlling a data transmission between said at least one primary unit, allocated to said bus, and said at least one secondary unit, addressed by said at least one primary unit, the data transmission being carried out selectively in one of a first data transmission configuration and a second data transmission configuration, the data transmission being split into a request data transfer and a response data transfer in the first data transmission configuration, and said bus being cleared for data transmissions of other primary units and secondary units in a time between the request data transfer and the response data transfer, said bus being blocked between the request data transfer and the response data transfer in the second data transmission configuration; and a logic circuit in said at least one primary unit and said at least one secondary unit linked to the bus system, for requesting, rejecting, and selecting the data transmission selectively in one of the first and second data transmission configurations. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27)
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28. In a microprocessor, a circuit arrangement for operating a bus system, comprising:
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at least one primary unit; at least one secondary unit; a bus between said at least one primary unit and said at least one secondary unit having at least one address bus, at least one data bus and at least one control line; at least one bus control unit controlling said bus and controlling a data transmission between said at least one primary unit, allocated to said bus, and said at least one secondary unit, addressed by said at least one primary unit, the data transmission being carried out selectively in one of a first data transmission configuration and a second data transmission configuration, the data transmission being split into a request data transfer and a response data transfer in the first data transmission configuration, and said bus being cleared for data transmissions of other primary units and secondary units in a time between the request data transfer and the response data transfer, said bus being blocked between the request data transfer and the response data transfer in the second data transmission configuration; and a logic circuit in said at least one primary unit and said at least one secondary unit linked to the bus system, for requesting, rejecting, and selecting the data transmission selectively in one of the first and second data transmission configurations.
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29. In a microcomputer, a circuit arrangement for operating a bus system, comprising:
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at least one primary unit; at least one secondary unit; a bus between said at least one primary unit and said at least one secondary unit having at least one address bus, at least one data bus and at least one control line; at least one bus control unit controlling said bus and controlling a data transmission between said at least one primary unit, allocated to said bus, and said at least one secondary unit, addressed by said at least one primary unit, the data transmission being carried out selectively in one of a first data transmission configuration and a second data transmission configuration, the data transmission being split into a request data transfer and a response data transfer in the first data transmission configuration, and said bus being cleared for data transmissions of other primary units and secondary units in a time between the request data transfer and the response data transfer, said bus being blocked between the request data transfer and the response data transfer in the second data transmission configuration; and a logic circuit in said at least one primary unit and said at least one secondary unit linked to the bus system, for requesting, rejecting, and selecting the data transmission selectively in one of the first and second data transmission configurations.
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Specification