×

System for interfacing between a plurality of processors having different protocols in switchgear and motor control center applications by creating description statements specifying rules

  • US 6,032,203 A
  • Filed: 04/07/1997
  • Issued: 02/29/2000
  • Est. Priority Date: 04/07/1997
  • Status: Expired due to Term
First Claim
Patent Images

1. A method for interfacing between a plurality of processors in a switchgear system, wherein at least two of the processors have different protocols, said method comprising the steps of:

  • a. defining an interface specification to govern the data exchange between the processors by the steps of;

    defining a list of one or more data blocks which define the characteristics of data coming from each processor, the data blocks comprising objects belonging to one or more object classes;

    defining a list of one or more data blocks destined for each processor, the data blocks defined in accordance with the protocol specification of the respective processor and comprising objects belonging to one or more object classes;

    defining a list of one or more logical and arithmetic functions to perform on the data blocks, the functions comprising objects belonging to one or more object classes;

    combining the data blocks and the functions from a first predetermined list into description statements specifying rules to interpret data coming from each processor;

    combining the data blocks and the functions from a second predetermined list into description statements specifying rules to create data destined for and meeting the protocol specification of each processor;

    b. creating a first software module to interpret the description statements and execute the rules in the description statements to interpret data coming from each processor and create data destined for and meeting the protocol specification of each processor; and

    c. creating a second software module to regulate the exchange of data between the processors such that any one of the processors is permitted to send data to or receive data from any other processor via the first software module.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×