Synchronous memory device utilizing two external clocks
First Claim
1. A synchronous memory device having a memory cell array having a plurality of subarrays, wherein each subarray includes a plurality of subarray sections, each subarray section includes a plurality of memory cells, the memory device comprising:
- clock receiver circuitry to receive first and second external clock signals from an external bus;
clock generation circuitry, coupled to the clock receiver circuitry, to generate a first internal clock signal having a clock edge which is synchronized with at least the first external clock signal and to generate a second internal clock signal having a clock edge which is synchronized with at least the second external clock signal;
a first subarray section, the first subarray section having a first internal I/O line to access data from a first memory cell location and a second internal I/O line to access data from a second memory cell location, wherein the first and second memory cell locations are in the first subarray section;
a second subarray section, the second subarray section having a first internal I/O line to access data from a third memory cell location and a second internal I/O line to access data from a fourth memory cell location, wherein the third and fourth memory cell locations are in the second subarray section;
output driver circuitry, including a first output driver and a second output driver, to output data onto the external bus in response to a read request; and
multiplexer circuitry, coupled to the output driver circuitry, wherein;
the multiplexer circuitry couples the first internal I/O line of the first subarray section to an input of the first output driver and couples the first internal I/O line of the second subarray section to an input of the second output driver in response to the clock edge of the first internal clock signal; and
the multiplexer circuitry couples the second internal I/O line of the first subarray section to an input of the first output driver and couples the second internal I/O line of the second subarray section to an input of the second output driver in response to the clock edge of the second internal clock signal.
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Abstract
A synchronous memory device includes clock receiver circuitry to receive first and second external clock signals from an external bus. Clock generation circuitry, coupled to the clock receiver circuitry, generates a first internal clock signal having a clock edge which is synchronized with at least the first external clock signal and generates a second internal clock signal having a clock edge which is synchronized with at least the second external clock signal. The memory device further includes a first subarray section and a second subarray section. The first subarray section includes a first internal I/O line to access data from a first memory cell location and a second internal I/O line to access data from a second memory cell location. The second subarray section includes a first internal I/O line to access data from a third memory cell location in the second subarray section and a second internal I/O line to access data from a fourth memory cell location in the second subarray section. The memory device also includes output driver circuitry, including a first output driver and a second output driver, to output data onto the external bus in response to the read request. Multiplexer circuitry couples the first internal I/O line of the first subarray section to an input of the first driver and couples the first internal I/O line of the second subarray section to an input of the second driver in response to a clock edge of a first internal clock signal; and couples the second internal I/O line of the first subarray section to an input of the first driver and couples the second internal I/O line of the second subarray section to an input of the second driver in response to the clock edge of the second internal clock signal.
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Citations
38 Claims
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1. A synchronous memory device having a memory cell array having a plurality of subarrays, wherein each subarray includes a plurality of subarray sections, each subarray section includes a plurality of memory cells, the memory device comprising:
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clock receiver circuitry to receive first and second external clock signals from an external bus; clock generation circuitry, coupled to the clock receiver circuitry, to generate a first internal clock signal having a clock edge which is synchronized with at least the first external clock signal and to generate a second internal clock signal having a clock edge which is synchronized with at least the second external clock signal; a first subarray section, the first subarray section having a first internal I/O line to access data from a first memory cell location and a second internal I/O line to access data from a second memory cell location, wherein the first and second memory cell locations are in the first subarray section; a second subarray section, the second subarray section having a first internal I/O line to access data from a third memory cell location and a second internal I/O line to access data from a fourth memory cell location, wherein the third and fourth memory cell locations are in the second subarray section; output driver circuitry, including a first output driver and a second output driver, to output data onto the external bus in response to a read request; and multiplexer circuitry, coupled to the output driver circuitry, wherein; the multiplexer circuitry couples the first internal I/O line of the first subarray section to an input of the first output driver and couples the first internal I/O line of the second subarray section to an input of the second output driver in response to the clock edge of the first internal clock signal; and the multiplexer circuitry couples the second internal I/O line of the first subarray section to an input of the first output driver and couples the second internal I/O line of the second subarray section to an input of the second output driver in response to the clock edge of the second internal clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A synchronous memory device having a memory cell array divided into a plurality of subarrays, including a first subarray and a second subarray wherein each subarray includes a plurality of subarray sections, the memory device comprises:
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clock receiver circuitry to receive first and second external clock signals from an external bus; clock generation circuitry, coupled to the clock receiver circuitry, to generate a first internal clock signal having a clock edge which is synchronized with the first external clock signal and to generate a second internal clock signal having a clock edge which is synchronized with the second external clock signal; interface circuitry coupled to the external bus to receive a read request; a first subarray section of a first subarray, the first subarray section having a first internal I/O line to access data from a first memory cell location and a second internal I/O line to access data from a second memory cell location, wherein the first and second memory cell locations are in the first subarray section; a second subarray section of a second subarray, the second subarray section having a first internal I/O line to access data from a third memory cell location and a second internal I/O line to access data from a fourth memory cell location, wherein the third and fourth memory cell locations are in the second subarray section; output driver circuitry, including a first output driver and a second output driver, to output data onto the external bus in response to the read request; and multiplexer circuitry, coupled to the output driver circuitry, wherein; the multiplexer circuitry couples the first internal I/O line of the first subarray section to an input of the first output driver and couples the first internal I/O line of the second subarray section to an input of the second output driver in response to the clock edge of the first internal clock signal; and the multiplexer circuitry couples the second internal I/O line of the first subarray section to an input of the first output driver and couples the second internal I/O line of the second subarray section to an input of the second output driver in response to the clock edge of the second internal clock signal. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. A memory system having a synchronous memory device coupled to a bus, the memory device having a memory cell array divided into a plurality of subarrays, wherein each subarray includes a plurality of subarray sections, the memory system comprises:
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clock receiver circuitry to receive first and second bus clocks from the bus; clock generation circuitry to generate a first clock edge which is synchronized with the first bus clock and to generate a second clock edge which is synchronized with the second bus clock; a first subarray section having a first data line to access data from a first memory cell location and a second data line to access data from a second memory cell location, wherein the first and second memory cell locations are in the first subarray section; a second subarray section having a first data line to access data from a third memory cell location and a second data line to access data from a fourth memory cell location, wherein the third and fourth memory cell locations are in the second subarray section; output drivers, including a first output driver and a second output driver, to output data onto the bus in response to a read request; and multiplexer circuitry, coupled to the output drivers, wherein; the multiplexer circuitry couples the first data line of the first subarray section to an input of the first output driver and couples the first data line of the second subarray section to an input of the second output driver in response to the first clock edge; and the multiplexer circuitry couples the second data line of the first subarray section to an input of the first output driver and couples the second data line of the second subarray section to an input of the second output driver in response to the second clock edge. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38)
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Specification