Multiprocessor with split transaction bus architecture providing cache tag and address compare for sending retry direction to other bus module upon a match of subsequent address bus cycles to content of cache tag

• US 6,032,231 A
• Filed: 03/09/1998
• Issued: 02/29/2000
• Est. Priority Date: 07/24/1995
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Unisys Corporation
• Inventors: Gujral, Manoj
• Primary Examiner(s): Cabeca, John W.
• Assistant Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US09/040,193
• Time in Patent Office: 722 Days
• Field of Search: 711/141, 711/145, 711/146, 711/142, 711/143, 395/296, 395/595, 395/847, 395/848
• US Class Current: 711/145
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)

Abstract

A method and system for arranging and operating a multiprocessor computer server system having "split-transaction bus" architecture, including bus modules operating with an address phase and a cycle phase. The bus modules are arranged for access by a prescribed resource stage to facilitate "RETRY" operations. The method includes providing a Cache Tag and Address Compare, arranging the system so that a first bus module stores the address for the Resource stage in the Cycle Tag; and comparing subsequent address bus cycles to the contents of the Cache Tag so that, given a "match", a "RETRY" direction is responsively sent to any other bus module that requests access. The system provides components supporting the above method steps.

Claims

1. A system for arranging and operating a multiprocessor computer server system having a "split-transaction bus" architecture, said multiprocessor computer server system including a plurality of bus module means operating with a bus cycle split into an address phase and a data phase, and arranged for access by at least one resource means, the resource means including requesting processor means, to facilitate "RETRY", said system also including:

Cache Tag means and Address Compare means, wherein said system is

arranged so that a first of said plurality of bus module means stores address for said Resource means in a Cycle Tag means;

means for comparing a further address corresponding to at least one subsequent address bus cycle to the address stored in the Cache Tag means; and

means for sending a "RETRY" direction to any other bus module means requesting access, as indicated when the address stored in the Cache Tag matches the further address, wherein said storing is effected when said Resource means completes the address phase, and wherein said Cache Tag means is arranged to support "cacheable lock" means arranged to perform load READ, WRITE sequences, including modifications thereof.

2. A system for arranging and operating a multiprocessor computer server system having "split-transaction bus" architecture, said system including a plurality of bus module means operating with an address phase and a cycle phase, and apt for accessed by prescribed resource means, to facilitate "RETRY", said system further including:

Cache Cycle Tag means and Address Compare means;

said system being arranged so that one of said plurality of bus module means stores the source-address, from said Resource means in said Cycle Tag means; and

means for comparing subsequent address bus cycles to the contents of said Cache Cycle Tag means so that

upon a "match", a suitable "RETRY" direction is sent to any other bus module means requesting access, wherein

said storing being effected when said resource means completes the address phase.

3. The system of claim 2, wherein said Resource means includes a requesting processor means.

4. The system of claim 2, wherein the related system bus cycle is split into an address phase and a data phase.

5. The system of claim 4, wherein said Resource means includes a requesting processor means.

6. The system of claim 2, wherein said Cache Tag means is arranged to support "cacheable lock" means arranged to perform load READ, WRITE sequences, including modifications thereof.

7. For a multiprocessor computer system having split-transaction bus architecture, a method for servicing a "WRITE-MISS" by performing a Write-Allocation of a desired cache line from system memory, said system including Cache Controller means, address bus means, data bus means, system memory means, and cache tag means, wherein:

cache controller means said is arranged to gain control of said address bus means; and

to generate an address cycle, wherein other cache controller means are arranged to snoop address for cache coherency or cycle hits; and

if all miss, said other cache controller means are arranged to

load cycle tag for write allocation cache line address;

then cause said cache controller means to begin monitoring said data bus means for cache line transfer;

then cause system memory means to gain control of said data bus means and to generate a data cycle; and

then cause said cache controller means to receive data transfer, to update cache tag entries, to dear cycle tag entry, and to retire said bus cycle.

8. The system of claim 7, wherein said Cache Tag means is arranged to support "cacheable lock" means arranged to perform load READ, WRITE sequences, including modifications thereof.

9. A method for using a computer system having "split-transaction bus" architecture, including a plurality of bus module means operating with an address phase and a cycle phase, and said computer system apt for accessed by prescribed resource means, to facilitate "RETRY", said method also involving:

providing Cache Tag means and Address Compare means;

arranging said system so that a first one of said bus module means stores the source-address, from said Resource means in said Cycle Tag means;

then compares subsequent address bus cycles to the contents of said Cache Tag means; and

then, upon a "match", sends a suitable "RETRY" direction to any other bus module means requesting access

wherein said storing is effected when said resource means completes the address phase.

10. The method of claim 9, wherein said Resource means includes a requesting processor means.

11. The method of claim 9, wherein said Cache Tag means is arranged to support "cacheable lock" means arranged to perform load READ, WRITE sequences, including modifications thereof.

12. A method of using a multiprocessor computer system having split-transaction bus architecture for servicing a "WRITE-MISS" by performing a Write-Allocation of a desired cache line from system memory, said method including providing a plurality of Cache Controller means, plus address bus means, plus system memory means, and cache tag means, said method further including:

arranging control means in said cache controller means to gain control of said address bus means, and to generate an address cycle, while other cache controllers snoop the address for cache coherency or cycle hits and all miss;

and arranging said controller means to thereupon load cycle tag for write allocation cache line address, so said cache controller can begin monitoring the data bus means for cache line transfer; and

providing system memory means arranged to gain control of data bus means, to generate cycle, wherein said cache controller means is arranged is arranged to receive data transfer; and

to update cache tag entries, while clearing cycle tag entry, and retiring bus cycle.

13. The method of claim 12, including arranging said Cache Tag means to support "cacheable lock" means arranged to perform load READ, WRITE sequences, including modifications thereof.

14. A method of arranging and operating a multiprocessor computer server system having "split-transaction bus" architecture, including bus modules operating with an address phase and a cycle phase, and arranged for accessed by a prescribed resource stage, to facilitate "RETRY", this method including:

providing Cache Tag means and Address Compare means;

arranging the system so that a first bus module stores the address for the Resource stage in the Cache Tag means; and

comparing subsequent address but cycles to the contents of the Cache Tag means, so that, given a "match", a "RETRY" direction is responsively sent to any other bus module that requests access.