Data processor with multiple compare extension instruction

• US 6,032,253 A
• Filed: 11/09/1998
• Issued: 02/29/2000
• Est. Priority Date: 06/15/1998
• Status: Expired due to Term

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Bahr, Raymond G., Cashman, John D., Ye, Wei, Riley, Paul M.
• Primary Examiner(s): Follansbee, John A.
• Application Number:
  US09/188,624
• Time in Patent Office: 477 Days
• Field of Search: 709/236, 710/105, 708/203, 712/300
• US Class Current: 712/300
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 69/18 Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
• CPC Class Codes: H04L 69/324 in the data link layer [OSI layer 2], e.g. HDLC
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A programmable data communications device is provided to process multiple streams of data according to multiple protocols. The device is equipped with a co-processor including multiple, programmable processors allowing data to be operated on by multiple protocols. The programmable processors within the co-processor include extended instruction sets including instructions providing the operations of zero stuffing, CRC computation, partial compare, conditional move, and trie traversal. These instructions allow the processor(s) of the co-processor to more efficiently execute programs implementing data communications protocols. Since each processor is programmable, protocols standards which change may be accommodated. A network device equipped with the co-processor can handle multiple simultaneous streams of data and can implement multiple protocols on each data stream. The protocols can execute within the co-processor either independently of each other, or in conjunction with each other.

Claims

1. A processor comprising:

a first input receiving a first input data, a second input receiving a second input data, a third input receiving a third input data and a multiple compare instruction;

a logic unit coupled to the first input, the second input, the third input and the multiple compare instruction, the logic unit including activatible multiple comparing circuitry which is activated upon receipt of the multiple compare instruction and which performs a comparison between the first input data and a series of predefined characters in the third input data, if the comparison results in the first input data being equal to any character in the series of predefined characters then a character match state is set;

a second logic unit coupled to the input, the second logic unit including activatible multiple comparing circuitry which is activated upon receipt of the multiple compare instruction and performs a comparison between the first input data and a predefined boundary, if the first input data is within the predefined boundary then a character boundary state is set if a mask bit in the second input data, at a position equal to the value in the first input data, is set on;

an output coupled to both the logic unit and the second logic unit, the output outputting the character match state and the character boundary state information; and

wherein the processor can be reprogrammed to execute a different one of many possible instructions.

2. The processor of claim 1 wherein the multiple compare instruction executes on the logic unit as part of a protocol to perform compression on the data.

3. The processor of claim 1 wherein the multiple compare instruction executes on the logic unit as part of a protocol to perform decompression on the data.

4. The processor of claim 1 wherein the multiple compare instruction executes on the logic unit as part of a protocol to perform encryption on the data.

5. The processor of claim 1 wherein the multiple compare instruction executes on the logic unit as part of a protocol to perform decryption on the data.

6. An apparatus comprising a computer readable medium having a multiple compare instruction recorded thereon, the multiple compare instruction comprising:

a first input receiving a first input data, a second input receiving a second input data, a third input receiving a third input data and a multiple compare instruction;

a logic unit coupled to the first input, the second input, the third input and the multiple compare instruction, the logic unit including activatible multiple comparing circuitry which is activated upon receipt of the multiple compare instruction and which performs a comparison between the first input data and a series of predefined characters in the third input data, if the comparison results in the first input data being equal to any character in the series of predefined characters then a character match state is set;

a second logic unit coupled to the input, the second logic unit including activatible multiple comparing circuitry which is activated upon receipt of the multiple compare instruction and performs a comparison between the first input data and a predefined boundary, if the first input data is within the predefined boundary then a character boundary state is set if a mask bit in the second input data, at a position equal to the value in the first input data, is set on;

an output coupled to both the logic unit and the second logic unit, the output outputting the character match state and the character boundary state information; and

wherein the processor can be reprogrammed to execute a different one of many possible instructions.

7. A method of processing data in a processor comprising the steps of:

coupling a first input data, a second input data, a third input data and a multiple compare instruction to a first logic unit and a second logic unit;

activating multiple comparing circuitry in the first logic unit upon receipt of the multiple compare instruction;

comparing the first input data and a series of predefined characters in the third input data;

if the comparison results in the first input data being equal to any character in the series of predefined characters then setting a character match state;

activating multiple comparing circuitry in the second logic unit upon receipt of the multiple compare instruction;

comparing the first input data with a predefined boundary;

if the first input data is within the predefined boundary then setting a character boundary state if a mask bit in the second input data, at a position equal to the value in the first input data, is set on;

outputting the character match state and the character boundary state; and

reprogramming the processor to execute one of many possible different instructions.

8. The processor of claim 7 wherein the multiple compare instruction executes on the logic units as part of a protocol to perform compression on the data.

9. The processor of claim 7 wherein the multiple compare instruction executes on the logic units as part of a protocol to perform decompression on the data.

10. The processor of claim 7 wherein the multiple compare instruction executes on the logic unit as part of a protocol to perform encryption on the data.

11. The processor of claim 7 wherein the multiple compare instruction executes on the logic unit as part of a protocol to perform decryption on the data.