Processor condition sensing circuits, systems and methods

• US 6,032,268 A
• Filed: 02/04/1992
• Issued: 02/29/2000
• Est. Priority Date: 09/04/1987
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Swoboda, Gary L., Ehlig, Peter N.
• Primary Examiner(s): Baker, Stephen M.
• Application Number:
  US07/832,661
• Time in Patent Office: 2,947 Days
• Field of Search: 371/16.2, 371/19, 371/22.3, 371/22.5, 714/30, 714/34, 714/726
• US Class Current: 714/30
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode
• CPC Class Codes: G01R 31/318342 by preliminary fault modelling, e.g. analysis, simulation
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318555 Control logic
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/2221 to test input/output devices or peripheral units
• CPC Class Codes: G06F 11/2236 to test CPU or processors
• CPC Class Codes: G06F 11/2289 by configuration test
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 11/263 Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
• CPC Class Codes: G06F 11/267 Reconfiguring circuits for testing, e.g. LSSD, partitioning
• CPC Class Codes: G06F 11/27 Built-in tests
• CPC Class Codes: G06F 11/2733 Test interface between tester and unit under test
• CPC Class Codes: G06F 11/3024 where the computing system component is a central processing unit [CPU]
• CPC Class Codes: G06F 11/3055 Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available error or fault processing without redundancy G06F11/0703; error detection or correction by redundancy in data representation G06F11/08; error detection or correction by redundancy in operation G06F11/14; error detection or correction by redundancy in hardware G06F11/16
• CPC Class Codes: G06F 11/3093 Configuration details thereof, e.g. installation, enabling, spatial arrangement of the probes
• CPC Class Codes: G06F 11/32 with visual or acoustical indication of the functioning of the machine
• CPC Class Codes: G06F 11/34 Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
• CPC Class Codes: G06F 11/36 Preventing errors by testing or debugging software
• CPC Class Codes: G06F 11/3636 : by tracing the execution of the program
• CPC Class Codes: G06F 11/3648 : using additional hardware
• CPC Class Codes: G06F 13/124 : where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
• CPC Class Codes: G06F 13/14 : Handling requests for interconnection or transfer
• CPC Class Codes: G06F 15/7842 : on one IC chip (single chip microcontrollers)
• CPC Class Codes: G06F 15/786 : using a single memory module
• CPC Class Codes: G06F 7/544 : for evaluating functions by calculation G06F7/4824 takes precedence
• CPC Class Codes: G06F 8/41 : Compilation
• CPC Class Codes: G06F 9/30 : Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/3001 : Arithmetic instructions
• CPC Class Codes: G06F 9/30021 : Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
• CPC Class Codes: G06F 9/30072 : to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30094 : Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/30101 : Special purpose registers
• CPC Class Codes: G06F 9/30141 : Implementation provisions of register files, e.g. ports
• CPC Class Codes: G06F 9/34 : Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes address translation G06F12/00
• CPC Class Codes: G06F 9/35 : Indirect addressing
• CPC Class Codes: G06F 9/462 : with multiple register sets

Abstract

The invention provides improved architectures and methods for emulation, simulation, and testability of data processing devices and systems without requiring physical probing or special test fixtures. A data processing device may include a semiconductor chip that is divided into domains. One domain may be halted and tested while another domain continues to operate. For example, the semiconductor chip may have a electronic processor domain and an analysis domain. The analysis domain may include an on-chip condition sensor that is connected to the electronic processor domain. The chip can further include control logic circuitry to allow the analysis domain to operate while the electronic processor is halted and tested.

Claims

1. A data processing device comprising:

a semiconductor chip;

an electronic processor on-chip;

an on-chip condition sensor connected to said electronic processor for analysis of the operations thereof, including means for recognizing the occurrence of a predetermined condition during real time operation of said electronic processor and means responsive to the recognition of said predetermined condition for applying a control input to said electronic processor during said real time operation thereof; and

a serial scan circuit connected to said on-chip condition sensor for inputting to said on-chip condition sensor control information which causes said on-chip sensor to assume a selected one of a plurality of sensing configurations;

wherein said on-chip sensor includes a plurality of sensor circuits responsive to particular internal conditions of said electronic processor and sensor circuit selection circuitry.

2. The device of claim 1 wherein said on-chip condition sensor includes a counter connectable to said sensor circuits.

3. The device of claim 2 wherein said serial scan circuit is interconnected with said counter for loading said counter with a value indicative of a predetermined count to which said condition sensor is thereby made sensitive.

4. The device of claim 2 wherein said on-chip condition sensor further includes a multiplexer having inputs connected to said sensor circuits and an output connected to said counter, the multiplexer making a selection responsive to said serial scan circuit.

5. The device of claim 1 wherein said sensor circuit selection circuitry includes a logic network connected to said sensor circuits, and said serial scan circuit is interconnected with said logic network for determining selections of sensor circuits by said logic network.

6. The device of claim 5, wherein said on-chip condition sensor includes a multiplexer having a plurality of inputs connected to said sensor circuits and having an output, and a counter having an input connected to said output of said multiplexer and having an output connected to said logic network.

7. The device of claim 6, wherein said multiplexer is connected to said serial scan circuit and is responsive to said serial scan circuit for connecting a selected one of said multiplexer inputs to said multiplexer output.

8. The device of claim 7, wherein said serial scan circuit is connected to said counter for loading said counter with a desired count value.

9. The device of claim 8, wherein one of said multiplexer inputs is connected to a clock signal which clocks said electronic processor for real time operations.

10. An electronic system comprising:

a data processing device including a semiconductor chip and an electronic processor on-chip;

a host computer external to said chip and connected to said data processing device, said host computer having a speed of operation which is slower than said electronic processor;

said data processing device further comprising an on-chip condition sensor coupled to said host computer, said on-chip condition sensor including means for recognizing the occurrence of a predetermined condition during real time operation of said electronic processor and means for stopping said electronic processor automatically upon occurrence of said predetermined condition; and

a serial scan circuit connected between said host computer and said on-chip condition sensor for inputting to said on-chip condition sensor control information which causes said on-chip condition sensor to assume a selected one of a plurality of sensing configurations;

wherein said on-chip condition sensor includes a plurality of sensor circuits responsive to particular internal conditions of said electronic processor, and a logic network connected to said sensor circuits, said serial scan circuit being supplied with command bits by said host computer and being interconnected with said logic network for determining selections of sensor circuits by said logic network.

11. An electronic system comprising:

a data processing device including a semiconductor chip and an electronic processor on-chip;

a host computer external to said chip and connected to said data processing device, said host computer having a speed of operation which is slower than said electronic processor;

said data processing device further comprising an on-chip condition sensor coupled to said host computer, said on-chip condition sensor including means for recognizing the occurrence of a predetermined condition during real time operation of said electronic processor and means for stopping said electronic processor automatically upon occurrence of said predetermined condition; and

a serial scan circuit connected between said host computer and said on-chip condition sensor for inputting to said on-chip condition sensor control information which causes said on-chip condition sensor to assume a selected one of a plurality of sensing configurations;

wherein said on-chip condition sensor includes sensor circuits responsive to particular internal conditions of said electronic processor, and a counter connectable to said sensor circuits, said serial scan circuit being interconnected with said counter for loading said counter from said host computer with a value indicative of a predetermined count to which said condition sensor is thereby made sensitive.

12. A method of performing real time monitoring of the operations of an electronic processor fabricated on a semiconductor chip, comprising the steps of:

providing a host computer having an operating speed which is lower than a real time operating speed of the electronic processor;

providing the electronic processor with an on-chip condition sensor for sensing real time operating conditions of said electronic processor;

loading the on-chip condition sensor from the host computer with information at said lower speed of the host computer to establish a desired sensing function to be executed by the on-chip condition sensor;

performing the desired sensing function in real time using the on-chip condition sensor, including the step of detecting whether a predetermined condition occurs during real time operation of the electronic processor; and

issuing a signal from the on-chip condition sensor to the electronic processor upon detection of the predetermined condition to make the electronic processor stop upon detection of the predetermined condition;

wherein the desired sensing function includes counting occurrences of selected conditions of the electronic processor and producing a signal when a predetermined count is reached.

13. A method of monitoring operations of a data processing device having an electronic processor fabricated on a semiconductor chip, the method comprising the steps of:

providing a program counter for holding an address of an instruction being processed by the electronic processor;

providing a program counter trace stack on chip;

identifying, during real time operation of said electronic processor, each instance wherein a pair of successive program counter addresses defines a discontinuity in execution by said electronic processor, and pushing both of said successive program counter addresses onto the program counter trace stack whenever a discontinuity occurs; and

transferring the contents of the program counter trace stack by serial scan-out to a host computer at a scan rate which is compatible with the speed of the host computer for monitoring purposes and slower than the real time speed of the electronic processor.

14. An electronic system comprising:

a data processing device including a semiconductor chip and an electronic processor on-chip, said electronic processor including a program counter for holding an address of an instruction being processed by said electronic processor;

a host computer off-chip and coupled to said data processing device, said host computer having a speed of operation which is slower than said electronic processor; and

said data processing device further comprising an on-chip trace stack, means for pushing onto said trace stack all pairs of successive program counter addresses that define a discontinuity in execution by said electronic processor, and a stack-full signaling circuit having an input connected to said trace stack.

15. The electronic system of claim 14 wherein said electronic processor comprises a digital signal processor.

16. The electronic system of claim 14 wherein said data processing device includes a serial scan circuit interconnected with said electronic processor and said on-chip trace stack.

17. The electronic system of claim 14 further comprising an on-chip program counter stack means for holding at least one address from which execution has been interrupted until operations return.

18. The electronic system of claim 14 further comprising means for storing respective bits corresponding to entries in said on-chip trace stack and representing whether each entry is a beginning or ending address of a discontinuity.