Method of forming a metal gate for CMOS devices using a replacement gate process

• US 6,033,963 A
• Filed: 08/30/1999
• Issued: 03/07/2000
• Est. Priority Date: 08/30/1999
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Shui-Hung, Su, Chi-Wen, Wu, Chung-Cheng, Huang, Jenn Ming
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): Pham, Long
• Application Number:
  US09/385,523
• Time in Patent Office: 190 Days
• Field of Search: 438/197, 438/299, 438/301, 438/303, 438/306, 438/307, 438/682, 438/683, 438/685, 257/368, 257/408
• US Class Current: 438/303
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A method of forming a metal gate for a CMOS device using a replacement gate process wherein sidewall spacers are formed on a dummy electrode prior to forming the metal gate allowing source and drain formation prior to metal gate formation and a tungsten layer is selectively deposited to act as an each or CMP stop and to reduce source and drain resistance. The process begins by forming a dummy gate oxide layer and a polysilicon dummy gate electrode layer on a substrate structure and patterning them to form a dummy gate. Lightly doped source and drain regions are formed by ion implantation using the dummy gate as an implant mask. Spacers are formed on the sidewalls of the dummy gate. Source and drain regions are formed by implanting ions using,the dummy gate and spacers as an implant mask and performing a rapid thermal anneal. A tungsten layer is selectively deposited on the dummy gate electrode and the source and drain regions. A blanket dielectric layer is formed over the dummy gate and the substrate structure. The blanket dielectric layer is planarized using a chemical mechanical polishing process stopping on the tungsten layer. The tungsten layer overlying the dummy gate and the dummy gate are removed, thereby forming a gate opening. A gate oxide layer and a metal gate electrode layer are formed in the gate opening. The gate electrode layer is planarized to form a metal gate, stopping on the blanket dielectric layer. Alternatively, the dummy gate electrode can be composed of silicon nitride and the selectively deposited tungsten layer can be omitted.

Claims

1. A method for forming a metal gate using a replacement gate process with a selective tungsten deposition comprising the steps of:

a. forming a dummy gate oxide layer on a substrate structure;

b. forming a dummy gate electrode layer on said dummy gate oxide layer;

said dummy gate electrode layer being composed of polysilicon;

c. patterning said dummy gate electrode layer and said dummy gate oxide layer to form a dummy gate having sidewalls;

d. implanting impurity ions into said substrate structure using said dummy gate as an implant mask;

e. forming spacers on said sidewalls of said dummy gate;

said spacers being composed of silicon dioxide or silicon oxynitride;

f. implanting impurity ions into said substrate structure using said dummy gate and said spacers as an implant mask and performing a rapid thermal anneal to form source and drain regions;

g. forming a selective tungsten layer on said dummy gate electrode and on said source and drain regions;

h. forming a blanket dielectric layer over said dummy gate and said substrate structure;

i. planarizing said blanket dielectric layer using a chemical mechanical polishing process and stopping on said tungsten layer;

j. removing said tungsten layer overlying said dummy gate and said dummy gate;

thereby forming a gate opening;

k. forming a gate oxide layer on said substrate structure in said gate opening;

l. forming a gate electrode layer over said gate oxide layer;

said gate electrode layer being composed of a metal selected from the group comprising titanium, tungsten, or aluminum; and

m. planarizing said gate electrode layer stopping on said blanket dielectric layer thereby forming a metal gate.

2. The method of claim 1 wherein said gate electrode is composed of a layer of tungsten over a layer of titanium nitride.

3. The method of claim 1 wherein said gate electrode is composed of a layer of aluminum over a layer of titanium nitride.

4. The method of claim 2 wherein said layer of titanium nitride has a thickness of between about 50 Angstroms and 500 Angstroms.

5. The method of claim 3 wherein said layer of titanium nitride has a thickness of between about 50 Angstroms and 500 Angstroms.

6. The method of claim 1 wherein said tungsten layer overlying said dummy gate and said dummy gate electrode are removed using a selective etch having a chlorine containing chemistry.

7. The method of claim 1 wherein said tungsten layer is formed by selective chemical vapor deposition at a temperature of between about 300°

C. and 500°

C. and a pressure of between about 50 mTorr and 500 mTorr using a chemistry of SiH₄ and WF₆.

8. The method of claim 7 wherein said tungsten layer is formed using a flow rate ratio of SiH₄ to WF₆ of between about 0.1 and 5.

9. A method for forming a metal gate using a replacement gate process with a selective tungsten deposition comprising the steps of:

a. providing a substrate structure having isolation structures thereon;

b. forming a dummy gate oxide layer on said substrate structure;

c. forming a dummy gate electrode layer on said dummy gate oxide layer;

said dummy gate electrode layer being composed of polysilicon;

d. patterning said dummy gate electrode layer and said dummy gate oxide layer to form a dummy gate comprising a dummy gate oxide and a dummy gate electrode and having sidewalls;

e. implanting As ions for lightly doped source and drain regions or highly doped source and drain extensions into said substrate structure at an energy of between about 1 KeV and 100 KeV and at a dose of between about 1E12 atm/cm² and 5E15 atm/cm² using said dummy gate as an implant mask;

f. forming spacers on said sidewalls of said dummy gate;

said spacers being composed of silicon dioxide or silicin oxynitride;

g. implanting As ions into said substrate stricture at an energy of between about 10 KeV and 100 KeV and at a dose of between about 1E15 atm/cm² and 8E15 atm/cm² using said dummy gate and said spacers as an implant mask and performing a rapid thermal anneal to form source and drain regions;

h. forming a selective tungsten layer on said dummy gate electrode and on said source and drain regions;

i. forming a blanket dielectric layer over said dummy gate and said substrate structure;

j. planarizing said blanket dielectric layer using a chemical mechanical polishing process using said tungsten layer for a chemical mechanical polishing stop layer;

k. removing said tungsten layer overlying said dummy gate and said dummy gate electrode using a selective etch;

thereby forming a gate opening;

l. removing said dummy gate oxide in said gate opening;

m. forming a gate oxide layer on said substrate structure in said gate opening;

n. forming a gate electrode layer over said gate oxide layer;

said gate electrode layer being composed of a metal selected from the group composed of titanium, tungsten, and aluminum;

o. planarizing said gate electrode layer stopping on said blanket dielectric layer thereby forming a gate electrode;

p. forming contacts at said source and drain regions by patterning said blanket dielectric layer to form contact openings and filling, said contact openings with conductive plugs; and

q. forming a first metal layer over said inter level dielectric and said conductive plugs.

10. The method of claim 9 wherein said gate electrode is composed of a layer of tungsten over a layer of titanium nitride.

11. The method of claim 9 wherein said gate electrode is composed of a layer of aluminum over a layer of titanium nitride.

12. The method of claim 10 wherein said layer of titanium nitride has a thickness of between about 50 Angstroms and 500 Angstroms.

13. The method of claim 11 wherein said layer of titanium nitride has a thickness of between about 50 Angstroms and 500 Angstroms.

14. The method of claim 9 wherein said tungsten layer overlying said dummy gate and said dummy gate electrode are removed using a selective etch having a chlorine containing chemistry.

15. The method of claim 9 wherein said tungsten layer is formed by selective chemical vapor deposition at a temperature of between about 300°

C. and 500°

C. and a pressure of between about 50 mTorr and 500 mTorr using a chemistry of SiH₄ and WF₆.

16. The method of claim 15 wherein said tungsten layer is formed using a flow rate ratio of SiH₄ to WF₆ of between about 0.1 and 5.

17. A method for forming a metal gate using a replacement gate process, comprising the steps of:

a. providing a substrate structure having isolation structures thereon;

b. forming a dummy gate oxide layer on said substrate structure;

c. forming a dummy gate electrode layer on said dummy gate oxide layer;

said dummy gate electrode layer being composed of silicon nitride;

d. patterning said dummy gate electrode layer and said dummy gate oxide layer to form a dummy gate comprising a dummy gate oxide and a dummy gate electrode and having sidewalls;

e. implanting impurity ions into said substrate structure using said dummy gate as an implant mask;

f. forming spacers on said sidewalls of said dummy gate;

said spacers being composed of silicon dioxide or silicin oxynitride;

g. implanting impurity ions into said substrate structure using said dummy gate and said spacers as an implant mask and performing a rapid thermal anneal to form source and drain regions;

h. forming a blanket dielectric layer over said dummy gate and said substrate structure;

i. planarizing said blanket dielectric layer using a chemical mechanical polishing process;

j. removing said dummy gate electrode using a wet etch;

thereby forming a gate opening;

k. removing said dummy gate oxide in said gate opening;

l. forming a gate oxide layer on said substrate structure in said gate opening;

m. forming a gate electrode layer over said gate oxide layer;

said gate electrode layer being composed of a metal selected from the group composed of titanium, tungsten, and aluminum;

n. planarizing said gate electrode layer stopping on said blanket dielectric layer thereby forming a gate electrode; and

o. forming an inter level dielectric layer over said gate electrode and said blanket dielectric layer.

18. The method of claim 17 wherein said gate electrode layer comprises a titanium nitride barrier layer having a thickness of between about 50 Angstroms and 500 Angstroms and a tungsten layer having a thickness of between about 50 Angstroms and 2000 Angstroms overlying said barrier layer.