Methods of operating ferroelectric memory devices having linear reference cells therein

• US 6,034,387 A
• Filed: 09/14/1999
• Issued: 03/07/2000
• Est. Priority Date: 06/17/1997
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Koo, Bon-jae
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US09/395,544
• Time in Patent Office: 175 Days
• Field of Search: 257/295, 257/296, 365/145, 365/149
• US Class Current: 257/295
• CPC Class Codes: G11C 11/22 using ferroelectric elements

Abstract

Nonvolatile ferroelectric-based integrated circuit memory devices utilize reference cells containing linear storage capacitors to inhibit deterioration in reliability typically associated with ferroelectric capacitors which have undergone excessive polarization cycling. These linear storage capacitors are preferably coupled to respective plate lines so that efficient reading operations may be performed. In particular, a nonvolatile memory device is preferably provided which contains a ferroelectric memory cell having an access transistor and a ferroelectric storage capacitor therein. A reference cell is also provided and this reference cell contains an access transistor and a linear storage capacitor therein. In addition, a sense amplifier is provided which has first and second inputs electrically coupled to the access transistors of the ferroelectric memory cell and the reference cell, respectively. To improve the efficiency of reading operations, a reset transistor is preferably provided and this transistor is electrically connected in series between the second input of the sense amplifier and a reference signal line (e.g., ground signal line).

Claims

1. A method of forming a ferroelectric memory device having a memory cell array and a reference cell array, comprising steps of:

a) forming a memory cell storage electrode and a ferroelectric layer pattern on a predetermined region of the memory cell array, and at the same time forming a reference cell storage electrode on a predetermined region of the reference cell array;

b) forming a dielectric layer pattern exposing the ferroelectric layer pattern; and

c) forming a memory cell plate electrode covering the exposed ferroelectric layer pattern, and a reference cell plate electrode covering the dielectric layer on the reference cell storage electrode.

2. The method of claim 18, wherein step a) comprises:

a1) sequentially forming a first conductive layer and a ferroelectric layer on a semiconductor substrate;

a2) patterning the ferroelectric layer, to form a ferroelectric layer pattern on a predetermined region of the first conductive layer of the memory cell array;

a3) forming a first photoresist pattern covering the ferroelectric layer pattern, and a second photoresist pattern covering a predetermined region of the first conductive layer of the reference cell array;

a4) etching the first conductive layer using the first and second photoresist patterns as an etching mask, to form a memory cell storage electrode and a reference cell storage electrode under the ferroelectric layer pattern and the second photoresist pattern, respectively; and

a5) removing the first and second photoresist patterns.

3. The method of claim 19, wherein the first conductive layer comprises platinum.