Ball grid array structure and method for packaging an integrated circuit chip

• US 6,034,427 A
• Filed: 01/28/1998
• Issued: 03/07/2000
• Est. Priority Date: 01/28/1998
• Status: Expired due to Fees

• Current Assignee: Prolinx Labs Corporation
• Original Assignee: Prolinx Labs Corporation
• Inventors: Xie, John Y., Jiang, Hang, Wu, Paul Y. F., Lan, James J. D., Chiang, Steve S., Shepherd, William H.
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): POTTER, ROY KARL
• Application Number:
  US09/014,693
• Time in Patent Office: 769 Days
• Field of Search: 257/701, 257/738, 257/746, 257/760, 257/774, 257/698
• US Class Current: 257/698
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48095 Kinked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48471 the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2224/48647 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/49431 on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/49433 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49883 : the conductive materials containing organic materials or pastes, e.g. for thick films for printed circuits H05K1/092
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01021 : Scandium [Sc]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0106 : Neodymium [Nd]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15173 : in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

An integrated circuit (IC) package substrate has a dielectric layer and a micro filled via formed substantially in the center of a hole in the dielectric layer. The IC package substrate has at least one chip bonding pad and one ball attach pad that are electrically coupled to each other by the micro filled via. The micro filled via is formed of a material called a "micro filled via material" that includes a binding material and optionally includes a number of particles (between 0%-90% by volume) dispersed in the binding material. The binding material can be any material, such as a polymer that is either conductive or nonconductive. The particles can be formed of any conductive material, such as a conductive polymer or a conductive metal (e.g. copper or gold). An electrical conductor can be originally formed simply by contact between conductive particles located adjacent to each other. In an optional step, the micro filled via is subjected to a programming current (in a step called "programming") to lower the resistance of an originally formed electrical conductor, or to originally form an electrical conductor by break down of a dielectric material. The IC package substrate can be formed in either a cavity up or a cavity down configuration.

Claims

1. A package for supporting at least one integrated circuit chip, said package having a first outer surface and a second outer surface opposite said first outer surface, said package comprising:

a dielectric layer located between said first outer surface and said second outer surface.

a plurality of chip bonding pads supported by at least said dielectric layer and formed in a first predetermined configuration suitable for connection to a plurality of pads on said integrated circuit chip;

a plurality of ball attach pads supported by at least said dielectric layer and formed in a second predetermined configuration;

an electrical conductor formed at least in the center of a hole defined by said dielectric layer, said electrical conductor being part of an electrical path between one of said ball attach pads and one of said chip bonding pads, said electrical conductor including at least one conductive particle and a binding material; and

a portion of an electrically conductive layer, said portion having a contiguous surface covering said hole, said contiguous surface being in contact with said electrical conductor.

2. The package of claim 1 wherein the resistance of said electrical conductor, after passage of a programming current through said conductive particle, is equal to or lower than the resistance of said electrical conductor before said passage.

3. The package of claim 1 wherein said binding material comprises a conductive polymer.

4. The package of claim 1 wherein said binding material comprises a nonconductive polymer.

5. The package of claim 1 wherein said portion has a substantially flat surface.

6. The package of claim 5 wherein said portion forms a trace.

7. The package of claim 5 wherein said portion forms one of said ball attach pads.

8. The package of claim 7 wherein said ball attach pad is substantially flat.

9. The package of claim 1 wherein said dielectric layer is devoid of woven glass fiber.

10. The package of claim 1 wherein said dielectric layer is devoid of drilled vias.

11. The package of claim 1 being devoid of BT core.

12. The package of claim 1 comprising a plurality of dielectric layers, each of said dielectric layers defining a hole, said package further comprising a plurality of electrical conductors formed at least in the center of the hole in each dielectric layer.

13. The package of claim 12 wherein at least two of said electrical conductors are substantially aligned with each other.

14. The package of claim 1 further comprising a plurality of traces formed in an inner layer, said inner layer being located between said first outer surface and said second outer surface, said inner layer being separated from said chip bonding pads by said dielectric layer, a trace of said plurality of traces being electrically connected to said electrical conductor, said trace being part of said electrical path.

15. The package of claim 14 further comprising a group of traces formed in a region of said first outer surface, the number of traces in said group being smaller than the number of traces in said plurality, each of said traces coupling one of said chip bonding pads to one of said ball attach pads.

16. The package of claim 1 further comprising an electrically conductive pattern formed in a region of said first outer surface, said pattern being formed in a predetermined configuration occupying an area completely surrounding each pad of a group of ball attach pads formed in said region, said region being predetermined for connection to a source of reference voltage.

17. The package of claim 16 wherein said group includes ball attach pads of at least one row.

18. The package of claim 16 wherein said group includes ball attach pads of a plurality of rows.

19. The package of claim 16 wherein said reference voltage is the ground reference voltage.

20. The package of claim 1 further comprising an electrically conductive pattern located between said first outer surface and said second outer surface, said pattern being formed in another predetermined configuration for connection to a power reference source.

21. The package of claim 1 further comprising a plurality of balls, each ball being attached to one of said ball attach pads.

22. The package of claim 1 wherein an electrically conductive path between said chip bonding pad and said ball attach pad consists essentially of said electrical conductor and a trace located between said first outer surface and said second outer surface.

23. The package of claim 1 further comprising a second electrical conductor formed in a second hole defined by said dielectric layer, wherein an electrically conductive path between said chip bonding pad and said ball attach pad consists essentially of said electrical conductor, a trace located between said first outer surface and said second outer surface, and said second electrical conductor.

24. The package of claim 1 further comprising a stiffener, wherein said stiffener supports said dielectric layer.

25. The package of claim 24 wherein a trace couples said chip bonding pad and said ball attach pad, said trace being located between said dielectric layer and said stiffener.

26. The package of claim 24 further comprising a heat sink, wherein said heat sink supports said stiffener.

27. A cavity up substrate for supporting at least one integrated circuit chip, said substrate having an exposed side and a contact side, said substrate comprising:

a first dielectric layer located between said contact side and said exposed side;

a second dielectric layer located between said contact side and said exposed side;

a plurality of chip bonding pads supported by at least said first dielectric layer and formed on said exposed side in a first predetermined configuration suitable for connection to a plurality of pads on said integrated circuit chip;

a plurality of ball attach pads supported by at least said second dielectric layer and formed on said contact side in a second predetermined configuration;

an electrical conductor formed at least in the center of a hole defined by said first dielectric layer, said electrical conductor being part of an electrical path between one of said ball attach pads and one of said chip bonding pads, said electrical conductor including at least one conductive particle and a binding material; and

a plated via formed in a hole defined by said second dielectric layer, said plated via being part of said electrical path.

28. The substrate of claim 27 wherein said electrical path consists essentially of said electrical conductor and said plated via.

29. The substrate of claim 27 wherein said electrical conductor in said dielectric layer has a diameter less than half the diameter of said plated via.

30. The substrate of claim 27 wherein said electrical conductor comprises a plurality of conductive particles, at least two of said conductive particles being in contact with each other.

31. The substrate of claim 27 having no more than one trace between two adjacent chip bonding pads.

32. A cavity down substrate for supporting at least one integrated circuit chip, said substrate having a contact side and an exposed side opposite said contact side, said substrate comprising:

a dielectric layer located between said contact side and said exposed side;

a plurality of chip bonding pads supported by at least said dielectric layer and formed on said contact side in a first predetermined configuration suitable for connection to a plurality of pads on said integrated circuit chip;

a plurality of ball attach pads supported by at least said dielectric layer and formed on said contact side in a second predetermined configuration;

an electrical conductor formed at least in the center of a hole defined by said dielectric layer, said electrical conductor being part of an electrical path between one of said ball attach pads and one of said chip bonding pads, said electrical conductor including at least one conductive particle and a binding material; and

a portion of an electrically conductive layer, said portion having a contiguous surface in contact with said electrical conductor, said contiguous surface covering said hole.

33. The substrate of claim 32 wherein said electrical conductor in said dielectric layer comprises a plurality of conductive particles, at least two of said conductive particles being in contact with each other.

34. The substrate of claim 32 having no more than one trace between two adjacent chip bonding pads.

35. A substrate for supporting at least one integrated circuit chip, said substrate comprising:

a dielectric layer; and

a plurality of chip bonding pads supported by at least said dielectric layer, a first group of said chip bonding pads being electrically connected to a first trace, wherein said first group of chip bonding pads are arranged in a row to interdigitate with a second group of said chip bonding pads, each chip bonding pad in said second group being physically located between two adjacent chip bonding pads in said first group.

36. The substrate of claim 35 wherein said first trace is predetermined for coupling to a source of the ground reference voltage.

37. The substrate of claim 35 wherein said first trace has a substantially square shape.

38. The substrate of claim 35 wherein the chip bonding pads in said second group are connected to a second trace, and said second trace is concentric with said first trace.

39. A substrate for supporting at least one integrated circuit chip, said substrate having a first outer surface and a second outer surface opposite said first outer surface, said substrate comprising:

a dielectric layer located between said first outer surface and said second outer surface;

a plurality of chip bonding pads supported by at least said dielectric layer, a first group of said chip bonding pads being formed in a first plane, and a second group of said chip bonding pads being formed in a second plane;

a plurality of ball attach pads supported by at least said dielectric layer;

an electrical conductor formed at least in the center of a hole defined by said dielectric layer, said electrical conductor being part of an electrical path between a chip bonding pad in said first plane and one of said ball attach pads, said electrical conductor including at least one conductive particle and a binding material; and

a portion of an electrically conductive layer, said portion having a contiguous surface in contact with said electrical conductor.

40. The substrate of claim 39 wherein all chip bonding pads in said second group are connected by traces in said second plane to a corresponding number of said ball attach pads.

41. The substrate of claim 39 wherein each chip bonding pad in said first group is coupled through an electrical conductor formed in the center of a hole defined by said dielectric layer to one of said ball attach pads.