L-connect routing of die surface pads to the die edge for stacking in a 3D array

• US 6,034,438 A
• Filed: 10/18/1996
• Issued: 03/07/2000
• Est. Priority Date: 10/18/1996
• Status: Expired due to Fees

• Current Assignee: Lawrence Livermore National Security LLC (Government of the United States of America)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: Petersen, Robert W.
• Primary Examiner(s): Picard, Leo P.
• Assistant Examiner(s): DUONG, HUNG V
• Application Number:
  US08/733,854
• Time in Patent Office: 1,236 Days
• Field of Search: 257/686, 257/786, 257/694-695
• US Class Current: 257/786
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Integrated circuit chips and method of routing the interface pads from the face of the chip or die to one or more sidewall surfaces of the die. The interconnection is routed from the face of the die to one or more edges of the die, then routed over the edge of the die and onto the side surface. A new pad is then formed on the sidewall surface, which allows multiple die or chips to be stacked in a three-dimensional array, while enabling follow-on signal routing from the sidewall pads. The routing of the interconnects and formation of the sidewall pads can be carried out in an L-connect or L-shaped routing configuration, using a metalization process such as laser pantography.

Claims

1. In an integrated circuit chip having a substrate with an interface surface and a side surface and with interface pads positioned entirely on an interface surface thereof, the improvement comprising:

a plurality of pads positioned entirely on at least one side surface which is traverse to said interface surface of said substrate, and

interconnects extending from said interface pads on said interface surface to said pads located entirely on said at least one side surface of said substrate.

2. The improvement of claim 1, wherein said interconnects are of an L-shaped configuration.

3. The improvement of claim 1, wherein said interconnects extend from said interface pads to the same, opposite, or neighboring side surfaces of said substrate.

4. The improvement of claim 1, additionally including a plurality of integrated circuit chips stacked on one another, and wherein at least certain of said pads on said side surfaces of the substrates are interconnected by interconnects extending between said pads.

17. The improvement of claim 4, additionally including a plurality of spacers interleaved between the adjacent chips.

5. A method of preparing integrated circuit die for stacking and interconnecting to produce a three-diminsional stack of circuit die, including:

forming interconnects on a surface of each die and on at least one sidewall of each die so as to be in contact with interface pads located entirely on the surface of each die and bonding pads located entirely on at least one sidewall of each die, thereby the circuit die when stacked on one another, can be interconnected via interconnected bonding pads located on the sidewall of each die.

6. The method of claim 5, wherein the bonding pads are formed integral with an end of an interconnect on the side wall of a die.

7. The method of claim 6, wherein forming of the interconnects is carried out using laser pantography.

8. The method of claim 5, wherein said bonding pads are formed using laser pantography.

9. The method of claim 5, additionally including stacking the circuit die on one another, and interconnecting at least certain of said bonding pads of the stacked circuit dies, thereby forming three-dimensional stacks of integrated circuit die.

10. The method of claim 7, additionally including forming the bonding pads on the sidewall of a die integral with the forming of the interconnects.

11. The method of claim 5, wherein the interconnects are of an L-shaped configuration.

12. An improved method of fabricating integrated circuit chips which enables stacking of the chips, comprising, routing of bonding pads on a surface on a die to a sidewall of a die;

and

forming bonding pads located entirely on the sidewall of the die and in contact with the interconnects.

13. The improved method of claim 12, additionally including forming of at least certain of the interconnects in an L-shaped configuration.

14. The improved method of claim 12, wherein forming of at least the interconnects is carried out using laser pantography.

15. The improved method of claim 12, additionally including forming at least one island on the surface of the die.

16. The improved method of claim 12, additionally including positioning a spacer between adjacent stacked chips.