Virtual logic system for reconfigurable hardware

• US 6,034,538 A
• Filed: 01/21/1998
• Issued: 03/07/2000
• Est. Priority Date: 01/21/1998
• Status: Expired due to Term

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Abramovici, Miron
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Chang, Daniel D.
• Application Number:
  US09/010,000
• Time in Patent Office: 776 Days
• Field of Search: 326/38, 326/39, 326/40, 326/41, 326/47, 326/37, 395/500.13-500.18, 395/500
• US Class Current: 326/38
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 2212/251 Local memory within processor subsystem
• CPC Class Codes: G06F 2212/253 Centralized memory

Abstract

A set of reconfigurable hardware includes a number of field programmable gate arrays (FPGAs), a controller referred to as a page manager, and a RAM-based local memory. In an illustrative embodiment, each of the FPGAs is suitable for implementing any one of a number of different portions of a logic circuit. A netlist or other descriptive information characterizing the logic circuit is partitioned into a number of pages, each of the pages corresponding to one of the portions of the circuit. The page manager controls the loading and unloading of the pages from the local memory into the FPGAs of the reconfigurable hardware, and controls storage and transfer of inter-page signals. The page manager is configured to detect "page faults" such as, for example, an unloaded page with a full input buffer. The page manager responds to a given page fault by subsequently loading the previously unloaded page into one of the FPGAs. The page manager may include FIFO input buffers or other suitable sets of registers for storing inter-page signal values for loaded and unloaded pages.

Claims

1. A method of reconfiguring a set of hardware to implement different portions of a circuit, the method comprising the steps of:

partitioning a model of the circuit into a plurality of pages, each of the pages corresponding to one of the portions of the circuit; and

controlling sequential loading of the pages from a memory into the hardware, such that detection of a condition relating to an unloaded page triggers a subsequent loading of the unloaded page.

2. The method of claim 1 wherein the condition relating to the unloaded page corresponds to an indication that an input buffer associated with the unloaded page is substantially full.

3. The method of claim 1 wherein the controlling step includes the step of storing inter-page signal values in first-in first-out buffers associated with the pages.

4. The method of claim 1 wherein the reconfigurable hardware includes a plurality of field programmable gate arrays, and the controlling step includes the step of controlling the loading of the pages such that a subset of the pages are loaded into the field programmable gate arrays.

5. The method of claim 4 wherein the controlling step includes controlling the loading of the pages such that a given page is loaded into different ones of the field programmable gate arrays at different times.

6. The method of claim 1 wherein the controlling step includes establishing a connection between a first page loaded into a first part of the reconfigurable hardware and an input buffer associated with a second page.

7. The method of claim 1 wherein the controlling step includes the steps of:

selecting a currently-loaded page to be replaced;

directing the disconnection of input and output lines in a portion of the reconfigurable hardware associated with the page to be replaced;

loading another page into the portion of the reconfigurable hardware;

retrieving previously-stored inter-page signal values associated with the other page; and

directing the connection of input and output lines associated with the other page.

8. A reconfigurable hardware apparatus comprising:

a plurality of reconfigurable devices, each capable of independently implementing a different portion of a circuit, wherein the circuit is characterized by a model partitioned into a plurality of pages, each of the pages corresponding to one of the portions of the circuit; and

a controller coupled to the reconfigurable devices, wherein the controller is operative to control loading of the pages into the devices, such that detection of a condition relating to an unloaded page triggers a subsequent loading of the unloaded page.

9. The apparatus of claim 8 wherein the condition relating to the unloaded page corresponds to an indication that an input buffer associated with the unloaded page is substantially full.

10. The apparatus of claim 8 further including a local memory coupled to the reconfigurable devices and the controller.

11. The apparatus of claim 8 wherein the controller is further operative to store inter-page signal values in first-in first-out buffers associated with the pages.

12. The apparatus of claim 8 wherein the reconfigurable devices are field programmable gate arrays, and the controller is further operative to control the loading of the pages such that a subset of the pages are loaded into the field programmable gate arrays.

13. The apparatus of claim 12 wherein the controller is further operative to control the loading of the pages such that a given page is loaded into different ones of the field programmable gate arrays at different times.

14. The apparatus of claim 8 wherein the controller is further operative to establish a connection between a first page loaded into a first one of the reconfigurable devices and an input buffer associated with a second page.

15. The apparatus of claim 8 wherein the controller and at least a subset of the reconfigurable devices are implemented on a circuit card connected to a host computer over a bus.

16. The apparatus of claim 8 wherein the controller is implemented at least in part using resources of a personal computer.

17. An apparatus for reconfiguring a set of hardware to implement different portions of a circuit, the apparatus comprising:

means for partitioning a model of the circuit into a plurality of pages, each of the pages corresponding to one of the portions of the circuit; and

means for controlling loading of the pages from a memory into the hardware, wherein one or more inter-page signal values directed from a given loaded page to an unloaded page are stored so as to be available for use when the unloaded page is subsequently loaded.

18. An apparatus for reconfiguring a set of hardware to implement different portions of a circuit, the apparatus comprising:

means for partitioning a model of the circuit into a plurality of pages, each of the pages corresponding to one of the portions of the circuit; and

means for controlling sequential loading of the pages from a memory into the hardware, such that detection of a condition relating to an unloaded page triggers a subsequent loading of the unloaded page.

19. A reconfigurable hardware apparatus comprising:

means for implementing different portions of a circuit using reconfigurable hardware, wherein the circuit is characterized by a plurality of pages, each of the pages corresponding to one of the portions of the circuit; and

means for controlling loading of the pages into the reconfigurable hardware, wherein one or more inter-page signal values directed from a given loaded page to an unloaded page are stored so as to be available for use when the unloaded page is subsequently loaded.

20. A reconfigurable hardware apparatus comprising:

means for implementing different portions of a circuit using reconfigurable hardware, wherein the circuit is characterized by a plurality of pages, each of the pages corresponding to one of the portions of the circuit; and

means for controlling sequential loading of the pages into the reconfigurable hardware, such that detection of a condition relating to an unloaded page triggers a subsequent loading of the unloaded page.

21. A method of reconfiguring a set of hardware to implement different portions of a circuit, the method comprising the steps of:

utilizing a plurality of reconfigurable devices to implement different portions of a circuit, wherein the circuit is characterized by a plurality of pages, with each of the pages corresponding to one of the portions of the circuit; and

controlling loading of the pages into the reconfigurable devices, such that one or more inter-page signal values directed from a given loaded page to an unloaded page are stored so as to be available for use when the unloaded page is subsequently loaded.

22. A method of reconfiguring a set of hardware to implement different portions of a circuit, the method comprising the steps of:

utilizing a plurality of reconfigurable devices to implement different portions of a circuit, wherein the circuit is characterized by a plurality of pages, each of the pages corresponding to one of the portions of the circuit; and

controlling sequential loading of the pages into the reconfigurable devices, such that an inter-page signal directed from a loaded page to an unloaded page is stored at least temporarily until a subsequent loading of the unloaded page.

23. An apparatus for implementing a circuit in reconfigurable hardware, comprising:

a circuit partitioner that partitions the circuit into non-pipelinable pages that can be implemented by said reconfigurable hardware; and

a memory for communicating results between a currently implemented one of said non-pipelinable pages and another of said non-pipelinable pages.

24. An apparatus for implementing a circuit in reconfigurable hardware, said circuit being partitioned into pages and a maximum size page of said pages being implementable on said reconfigurable hardware, said apparatus comprising:

a page manager for controllably supplying said pages into said reconfigurable hardware in an arbitrary order, wherein said page manager swaps said pages so as to implement said circuit; and

a memory for communicating results between a currently implemented one said pages and another of said pages.

25. A reconfigurable hardware apparatus comprising:

a plurality of reconfigurable devices, each capable of independently implementing a different portion of a circuit, wherein the circuit is characterized by a model partitioned into a plurality of pages, each of the pages corresponding to one of the portions of the circuit; and

a controller coupled to the reconfigurable devices, wherein the controller is operative to control loading of the pages into the devices, such that one or more inter-page signal values directed from a given loaded page to an unloaded page are stored so as to be available for use when the unloaded page is subsequently loaded.