Bus structure for modularized chip with FPGA modules
First Claim
1. An integrated circuit device comprising:
- a bus comprising a plurality of bus lines;
a plurality of modules, at least one of the modules comprising an FPGA, the FPGA comprising;
a plurality of configurable logic blocks; and
a plurality of interconnect lines for interconnecting the logic blocks;
for each module, an associated interface structure for driving signals from the module onto the bus lines and for applying signals on the bus lines to the modulemeans for configuring the bus and the FPGA; and
a bus arbiter coupled to the bus for selecting which of the interface structures can drive signals onto the bus.
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Accused Products
Abstract
An on-chip bus structure for use in a modularized integrated circuit chip including an FPGA module(s). The bus is intended for memory mapped data transfers between circuit modules, for instance master, slave, master/slave, bus controller, and bus monitor type modules. Each circuit module is an on-chip function block including a bus interface and communicates by a predefined set of bus signals; at least one module is an FPGA (field programmable gate array). Each module acts as a bus master when it initiates data read or write operations, or may be addressed during a bus read/write operation and thereby acts as a bus slave. This bus and module structure allows implementation of a system on a single chip.
249 Citations
27 Claims
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1. An integrated circuit device comprising:
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a bus comprising a plurality of bus lines; a plurality of modules, at least one of the modules comprising an FPGA, the FPGA comprising; a plurality of configurable logic blocks; and a plurality of interconnect lines for interconnecting the logic blocks; for each module, an associated interface structure for driving signals from the module onto the bus lines and for applying signals on the bus lines to the module means for configuring the bus and the FPGA; and a bus arbiter coupled to the bus for selecting which of the interface structures can drive signals onto the bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. An integrated circuit device comprising:
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a bus comprising a plurality of bus lines; a plurality of modules, at least one of the modules comprising an FPGA, the FPGA comprising; a plurality of configurable logic blocks, and a plurality of interconnect lines for interconnecting the logic blocks; for each module, an associated interface structure for driving signals from the module onto the bus lines and for applying signals on the bus lines to the module; and means for configuring the bus and the FPGA; wherein at any time only one master of the interface structures drives signals onto the bus and the master selects which of the interface structures can receive signals from the bus.
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17. An integrated circuit device comprising:
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a bus comprising a plurality of bus lines; a plurality of modules, at least one of the modules comprising an FPGA, the FPGA comprising; a plurality of configurable logic blocks, and a plurality of interconnect lines for interconnecting the logic blocks; for each module, an associated interface structure for driving signals from the module onto the bus lines and for applying signals on the bus lines to the module; and means for configuring the bus and the FPGA; wherein at any time one of the modules is a master and each of the interface structures decodes a command from the master to detect when the associated interface structure is to receive signals from the bus.
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18. An integrated circuit device comprising:
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a bus comprising a plurality of bus lines; a plurality of modules, at least one of the modules comprising an FPGA, the FPGA comprising; a plurality of configurable logic blocks, and a plurality of interconnect lines for interconnecting the logic blocks; for each module, an associated interface structure for driving signals from the module onto the bus lines and for applying signals on the bus lines to the module; and means for configuring the bus and the FPGA; wherein the interface structures comprise a plurality of masters and each of the masters determines bus availability upon needing the bus and becomes a driver when the bus is found to be idle.
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19. An integrated circuit device comprising:
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a plurality of FPGA modules; a bus interconnecting the FPGA modules; and a bus arbiter coupled to the bus for selecting which of the FPGA modules can drive signals onto the bus. - View Dependent Claims (20, 21, 22, 23, 24)
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25. An integrated circuit device comprising:
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a plurality of FPGA modules; and a bus interconnecting the FPGA modules; wherein at any time only one master of the FPGA modules structures drives signals onto the bus and the master selects which of the FPGA modules can receive signals from the bus.
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26. An integrated circuit device comprising:
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a plurality of FPGA modules; and a bus interconnecting the FPGA modules; wherein at any time one of the FPGA modules is a master and each of the FPGA modules decodes a command from the master to detect when the associated FPGA module is to receive signals from the bus.
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27. An integrated circuit device comprising:
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a plurality of FPGA modules; and a bus interconnecting the FPGA modules; wherein the FPGA modules comprise a plurality of masters and each of the masters determines bus availability upon needing the bus and becomes a driver when the bus is found to be idle.
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Specification