Multi-state flash memory defect management

• US 6,034,891 A
• Filed: 12/01/1997
• Issued: 03/07/2000
• Est. Priority Date: 12/01/1997
• Status: Expired due to Term

• Current Assignee: Micron Quantum Devices Inc (Micron Technology, Inc.)
• Original Assignee: Micron Technology, Inc.
• Inventors: Norman, Robert D.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US08/980,528
• Time in Patent Office: 827 Days
• Field of Search: 365/200, 365/189.07, 365/185.03, 365/185.33, 365/185.09, 365/185.11, 395/182.04, 395/182.05, 371/11.1, 371/10.1, 371/10.2
• US Class Current: 365/185.09
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 29/82 for EEPROMs

Abstract

A system is described which stores data intended for defective memory cells in a row of a memory array in an overhead location of the memory row. The data is stored in the overhead packet during a write operation, and is read from the overhead packet during a read operation. A defect location table for the row of the memory array is provided to identify when a defective memory cell is address;ed for either a read or write access operation. During a write operation, the correct data is stripped from incoming data for storing into the overhead packet. During a read operation, the correct data is inserted into an output data stream from the overhead packet. Data written to defective cells can be either a custom setting, a default setting, or the original data. Shift registers are described for holding good data during either a read or write operation. The number of shift registers used is determined by the number of states stored in a memory cell. The shift registers use a marker for alignment ofdata bits in a data stream.

Claims

1. A processing system comprising

a plurality of flash memory devices each having an array of memory cells arranged in rows and columns, each row of the array including overhead memory cells to store overhead data;

a processor to control read and write operations for the plurality of flash memory devices;

a defect table register to store a defect table including addresses of defective memory cells in the plurality of flash memory devices;

a compare circuit to compare the defect table and an address of a memory location of one of the plurality of flash memory devices to determine if the memory location is defective;

at least one shift register to serially hold input data intended to be written to defective memory locations; and

memory interface logic to store contents of the at least one shift register in the overhead memory cells.

2. The processing system of claim 1, further comprising a read shift register to serially hold output data intended to read from the defective memory locations, such that the memory interface logic reads contents of the overhead memory cells and stores the contents in the read shift register.

3. The processing system of claim 1 wherein the at least one shift register is adapted to serially hold output data read from the defective memory locations, Such that the memory interface logic reads contents of the overhead memory cell and stores the contents in the at least one shift register.

4. The processing system of claim 1 wherein each of the memory cells in the plurality of flash memory devices store X-bits of data.

5. The processing system of claim 4 wherein the at least one shift register comprises X shift registers.

6. The processing system of claim 1 wherein the memory interface logic includes elements to store a marker in the at least one shift register for aligning data stored therein.

7. The processing system of claim 6 wherein the marker is a logic zero data bit.

8. The processing system of claim 1, further comprising substitution circuitry to replace the input data intended to be written to the defective memory locations with predetermined substitution data.

9. The processing system of claim 8 wherein the substitution circuitry comprises a multiplex circuit.

10. The processing system of claim 1 wherein each of the memory cells of the plurality of flash memory devices store n-bits of data and the at least one shift register comprises n shift registers.

11. The processing system of claim 1 wherein the defect table includes predetermined substitution data for replacing the input data intended to be written to the defective memory locations.

12. The processing system of claim 11 wherein the predetermined substitution data is encoded for n-state data storage.

13. The processing system of claim 1 wherein the defect table includes addresses of defective memory cells located in a single row.

14. The processing system of claim 1 wherein the defect table is stored in one of the plurality of flash memory devices for use by the defect table register.

15. A method of storing data in a flash memory device comprising an array of memory cells arranged in rows and columns, each row of the array having a data portion for storing data, and an overhead portion, the method comprising:

identifying defective memory cells located in the data portion of a row;

receiving a stream of data bits to be stored in the array of memory cells;

selectively removing data bits from the data stream which are intended to be written to the defective memory cells; and

serially storing the removed data bit in the overhead portion of the row.

16. The method of claim 15 wherein selectively removing data bits from the data stream further comprises holding the removed data bits in at least one shift register.

17. The method of claim 15 further comprising:

storing a marker in at least one shift register; and

storing the removed data bits in the at least one shift register and aligning the data bits with the marker.

18. The method of claim 17 wherein the marker is a logic zero data bit.

19. The method of claim 17, further comprising storing n-bits of the data bits in each memory cell in the array of memory cells.

20. The method of claim 15 further comprising:

replacing the removed data bits with substitution data bit; and

storing the stream of data bits including the substitution data bits in the array of memory cells.

21. The method of claim 15 further comprising:

creating a defect table comprising addresses of the defective memory cells.

22. The method of claim 21 wherein selectively removing data bits comprises:

comparing the addresses of the defective memory cells from the defect table with addresses of accessed memory cells; and

indicating when the compared addresses match.

23. The method of claim 21, further comprising adding substitution data to the defect table to replace the removed data bits.

24. A method of storing and retrieving data in a memory device, the method comprising:

receiving an input serial stream of data bits, and storing the input serial stream of data bits in a data location of the memory device wherein at least two of the data bits are stored in one memory cell;

selectively copying data bits from the input serial stream of data bits and storing the copied data bits in an overhead location of the memory device;

reading an output serial stream of data bits stored in the data location of the memory device;

reading the copied data bits from the overhead location of the memory device; and

selectively replacing data bits in the output serial stream of data bits to recreate the received input serial stream of data bits.

25. The method of claim 24, further comprising:

comparing an address of the data location of the memory device with addresses of known defective memory cells; and

identifying the data bits which are selectively copied.

26. The method of claim 24, further comprising placing the selectively copied data bits in a shift register prior to storing the copied data bits in the overhead location.

27. The method of claim 24, further comprising:

storing a marker in at least one shift register; and

storing the selectively copied data bits in the at least one shift register and aligning the data bits with the marker.

28. The method of claim 27 wherein storing a marker comprises storing a logic zero data bit in at least one shift register.

29. The method of claim 27 wherein;

receiving an input serial stream further comprises storing n bits of the data bits in each memory cell in which the data bits are stored; and

storing a marker comprises n makers respectively in n shift registers.

30. The method of claim 24 wherein;

wherein selectively copying further comprises placing the copied data bits in two shift registers prior to storing the copied data bits; and

receiving an input serial steam further comprises storing two bits of the data bits in each memory cell in which the data bits are stored.

31. The method of claim 24 wherein selectively replacing data bits further comprises replacing the data bits using a multiplex circuit.

32. A method of storing data in a memory device, the method comprising:

selecting a current access target location in the memory device;

comparing a table of known defective memory cell locations in the memory device to the current access target location in the memory device;

extracting data bits from a plurality of data bits to be stored in the current access target location in the memory device;

substituting alternate data bits for the extracted data bits;

storing the plurality of data bits including the alternate data bits in the current access target location; and

storing the extracted data bits in the memory device in a second location.

33. The method of claim 32, further comprising storing the alternate data bits in the table of known defective memory cell locations.

34. The method of claim 32 wherein substituting alternate data bits further comprises substituting the alternate data bits using a multiplex circuit.

35. The method of claim 32, further comprising holding the extracted data bits in at least one shift register prior to storing the extracted data bits in the memory device in a second location.

36. The method of claim 32, further comprising providing the alternate data bits from a controller.

37. A method of defect management in a memory device having a row of memory cells arranged in n-data packets including at least one overhead data packet, the method comprising:

identifying memory cells located in the n-data packets which are defective; and

rerouting data intended to be stored in the defective memory cells to be stored in the at least one overhead data packet.

38. The method of claim 37 wherein each data packet has 32 bytes of memory cells.

39. The method of claim 37 wherein each memory cell stores at least two data bits.

40. The method of claim 39 wherein rerouting data further comprises holding the data in two shift registers.

41. The method of claim 37 wherein rerouting data further comprises holding the data in at least one shift register.

42. A data management system comprising:

a controller to access memory locations in memory devices in response to externally provided commands;

a defect table register to store a defect table having a plurality of memory addresses of defective memory locations;

a comparator to compare addresses stored in the defect table to currently accessed memory addresses;

a plurality of shift registers to store data directed to the defective memory locations; and

substitution circuitry to selectively substitute data in place of the data stored in the shift registers.

43. The data management system of claim 42 wherein the substitution circuitry comprises a multiplex circuit coupled to the controller and a memory device interface.

44. The data management system of claim 42 wherein each of the memory locations stores X bits of data.

45. The data management system of claim 44 wherein the shift registers comprise X shift registers.

46. The data management system of claim 42 wherein the defect table comprises data to be substituted in place of the data stored in the shift registers.

47. The data management system of claim 42 wherein the memory devices comprise a plurality of flash memories.

48. The data management system of claim 42, further comprising a multiplex circuit coupled to the plurality of shift registers to route even and odd data bits to the plurality of shift registers.

49. A processing system comprising:

a plurality of n-state flash memory devices each having an array of memory cells arranged in rows and columns, each row of each array including memory cells dedicated to storing overhead data;

a processor to control read and write operations for the plurality of n-state flash memory devices;

a defect table register to store a defect table containing addresses of defective memory cells in the plurality of n-state flash memory devices and to store replacement data;

a compare circuit to compare the addresses of the defect table and an address of a memory location of one of the plurality of n-state flash memory devices to determine if the memory location is defective;

n-shift registers to serially hold input data intended to be written to defective memory locations;

substitution circuitry to substitute the replacement data from the defect table in place of the input data intended to be written to defective memory locations prior to writing the input data to one of the n-state flash memory devices; and

memory interface logic to store contents of the n-shift registers in the memory cells dedicated to storing overhead data.

50. A processing system comprising:

a flash memory device having an array of memory cells arranged in rows and columns, each row in the array including memory cells to store input data and overhead memory cells to store overhead data;

a processor to control read and write operations for the flash memory device; and

a remapping circuit coupled between the flash memory device and the processor to transfer data to and from the flash memory device, the remapping circuit comprising;

a register containing a defect table with addresses of defective memory cells in the flash memory device;

a compare circuit to compare the addresses in the defect table and an address of a selected memory cell in the flash memory device to determine if the selected memory cell is defective;

at least one shift register to hold input data intended to be written to the defective memory cells in the flash memory device; and

interface logic to write contents of the shift register to the overhead memory cells.

51. The processing system of claim 50 wherein the flash memory device comprises a plurality of flash memory devices coupled to the remapping circuit.