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Multi-state flash memory defect management

  • US 6,034,891 A
  • Filed: 12/01/1997
  • Issued: 03/07/2000
  • Est. Priority Date: 12/01/1997
  • Status: Expired due to Term
First Claim
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1. A processing system comprisinga plurality of flash memory devices each having an array of memory cells arranged in rows and columns, each row of the array including overhead memory cells to store overhead data;

  • a processor to control read and write operations for the plurality of flash memory devices;

    a defect table register to store a defect table including addresses of defective memory cells in the plurality of flash memory devices;

    a compare circuit to compare the defect table and an address of a memory location of one of the plurality of flash memory devices to determine if the memory location is defective;

    at least one shift register to serially hold input data intended to be written to defective memory locations; and

    memory interface logic to store contents of the at least one shift register in the overhead memory cells.

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