Space management for managing high capacity nonvolatile memory

• US 6,034,897 A
• Filed: 04/01/1999
• Issued: 03/07/2000
• Est. Priority Date: 04/01/1999
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Lexar Media Incorporated (Micron Technology, Inc.)
• Inventors: Guo, Min, Estakhri, Petro, Iman, Berhanu
• Primary Examiner(s): Dinh, Son T.
• Application Number:
  US09/283,728
• Time in Patent Office: 341 Days
• Field of Search: 365/185.29, 365/185.33, 365/218, 365/230.03
• US Class Current: 365/185.33
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

In accordance with an embodiment of the present invention, a controller device is disclosed for use in a digital system having a host and nonvolatile memory devices. The controller device is coupled to the host and at least two nonvolatile memory devices. The host stores digital information in the nonvolatile memory unit and reads the stored digital information from the nonvolatile memory unit under the direction of the controller, the memory unit being organized into blocks of sectors of information. The controller device erases the digital information stored in the blocks of the nonvolatile memory devices in-parallel form. The controller device includes a space manager circuit responsive to address information from the host and operative to read, write or erase information in the nonvolatile memory unit based upon the host address information. The space manager assigns a predetermined number of blocks, in sequential order, to each of the nonvolatile memory devices, forms `super` blocks, each `super` block having blocks arranged inparallel, identifies a particular `super` block having at least two blocks, a first block being located in a first nonvolatile memory device and a second block being located in a second nonvolatile memory device, for erasure of the particular `super` block. The first block within the first nonvolatile memory device is first selected for erasure thereof and an erase operation to be performed on the selected first block is initiated. Thereafter, a second block within the second nonvolatile memory device is selected for erasure thereof and an erase operation to be performed on the selected second block is initiated. Thereafter, the first and second block of the particular `super` block are erased so that erasure of the second block is performed without waiting for completion of the erasure of the first block. The status of the first and second nonvolatile memory devices is indicated as being busy during erasure of the first and second blocks, wherein the speed of erase operations in the digital system is substantially increased due to the blocks of the `super` block being arranged in-parallel and overlapping of the erase operations of the blocks within the `super` blocks thereby increasing the overall performance of the digital system.

Claims

1. A method for use in a digital system having a controller device coupled to a host and at least two nonvolatile memory devices, the host for storing digital information in the nonvolatile memory unit and reading the stored digital information from the nonvolatile memory unit under the direction of the controller, the memory unit being organized into blocks of sectors of information, the method for erasing digital information stored in the blocks of the nonvolatile memory devices inparallel and comprising:

(a) assigning a predetermined number of blocks, in sequential order, to each of the nonvolatile memory devices, each block having a predetermined number of sectors;

(b) forming `super` blocks, each `super` block having blocks arranged in parallel wherein blocks of the same sequential number in each of the nonvolatile memory devices in like position relative to each other;

(c) identifying a particular `super` block having at least two blocks, a first block being located in a first nonvolatile memory device and a second block being located in a second nonvolatile memory device, for erasure of the particular `super` block by the controller;

(d) first selecting the first block within the first nonvolatile memory device from the particular `super` block for erasure thereof;

(e) initiating an erase operation to be performed on the selected first block;

(f) second selecting a second block within the second nonvolatile memory device from the particular `super` block for erasure thereof;

(g) initiating an erase operation to be performed on the selected second block;

(h) erasing the first and second block of the particular `super` block so that erasure of the second block is performed without waiting for completion of the erasure of the first block; and

(h) indicating the status of the first and second nonvolatile memory devices to be busy during erasure of the first and second blocks,

wherein the speed of erase operations in the digital system is substantially increased due to the blocks of the `super` block being arranged in-parallel and overlapping of the erase operations of the blocks within the `super` blocks thereby increasing the overall performance of the digital system.

2. A method for use in a digital system as recited in claim 1 further including the steps of setting an erase counter equal to the number of blocks within a `super` block and decrementing the erase counter after each of the initiating steps.

3. A method for use in a digital system as recited in claim 2 wherein upon the value indicated by the erase counter reaching `0`, checking for completion of the erasure of all of the blocks within the particular `super` block.

4. A method for use in a digital system as recited in claim 1 wherein during the indicating step, setting a Ready/Busy* signal for indicating that the nonvolatile memory unit is busy upon starting the erase operation on the first nonvolatile memory device and upon completion of the erase operation on the last nonvolatile memory device of the nonvolatile memory unit, resetting the Ready/Busy* signal for indicating that the nonvolatile memory unit is not longer busy.

5. A method for use in a digital system as recited in claim 1 further including completing erasing of all of the selected blocks within the particular super block and thereafter verifying successful completion of the selected blocks of the particular super block.

6. A method for use in a digital system as recited in claim 5 wherein said verifying step includes issuing a read status command.

7. A method for use in a digital system as recited in claim 1 wherein the particular super block includes more than two blocks and selecting the more than two blocks for erasure thereof, erasing the same and upon completion of the erasure, verifying erasure thereof.

8. A controller device for use in a digital system, the controller device being coupled to a host and at least two nonvolatile memory devices, the host for storing digital information in the nonvolatile memory unit and reading the stored digital information from the nonvolatile memory unit under the direction of the controller, the memory unit being organized into blocks of sectors of information, the controller device for erasing digital information stored in the blocks of the nonvolatile memory devices in parallel and comprising:

a space manager circuit responsive to address information from the host and operative to read, write or erase information in the nonvolatile memory unit based upon the host address information, the space manager for assigning a predetermined number of blocks, in sequential order, to each of the nonvolatile memory devices, for forming `super` blocks, each `super` block having blocks arranged inparallel wherein blocks of the same sequential number in each of the nonvolatile memory devices in like position relative to each other, for identifying a particular `super` block having at least two blocks, a first block being located in a first nonvolatile memory device and a second block being located in a second nonvolatile memory device, for erasure of the particular `super` block, for first selecting the first block within the first nonvolatile memory device from the particular `super` block for erasure thereof, for initiating an erase operation to be performed on the selected first block, for second selecting a second block within the second nonvolatile memory device from the particular `super` block for erasure thereof, for initiating an erase operation to be performed on the selected second block, erasing the first and second block of the particular `super` block so that erasure of the second block is performed without waiting for completion of the erasure of the first block, and for indicating the status of the first and second nonvolatile memory devices to be busy during erasure of the first and second blocks,

wherein the speed of erase operations in the digital system is substantially increased due to the blocks of the `super` block being arranged in-parallel and overlapping of the erase operations of the blocks within the `super` blocks thereby increasing the overall performance of the digital system.

9. A controller device for use in a digital system as recited in claim 8 further including a flag field for indicating the status of the particular super block for use in identifying the particular super block as being `old` and ready for erasure thereof by the controller device.

10. A controller device for use in a digital system as recited in claim 8 further including an erase counter and for setting the erase counter equal to the number of blocks within a `super` block prior to the start of the erase operation on the particular super block and decrementing the erase counter after starting erasure of each of the blocks of the particular super block.

11. A controller device for use in a digital system as recited in claim 10 wherein upon the value indicated by the erase counter reaching `0`, the controller device for checking for completion of the erasure of all of the blocks within the particular `super` block.

12. A controller device for use in a digital system as recited in claim 8 wherein the nonvolatile memory devices are flash chips.