Method of operating a memory having a variable data output length and a programmable register

• US 6,034,918 A
• Filed: 02/19/1999
• Issued: 03/07/2000
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US09/252,997
• Time in Patent Office: 382 Days
• Field of Search: 365/233, 365/235, 365/238.5, 395/878, 395/880, 395/856
• US Class Current: 365/233.12
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method of controlling a memory device is disclosed wherein the memory device includes a plurality of memory cells. The method comprises providing first block size information to the memory device, wherein the first block size information defines a first amount of data to be output onto a bus in response to a read request. The method further includes issuing a first read request to the memory device, wherein in response to the first read request, the memory device outputs the first amount of data corresponding to the first block size information onto the bus synchronously with respect to an external clock signal. In one preferred embodiment, the method may include providing a code which is representative of a number of clock cycles of the first and second external clock which are to transpire before data is output by the memory device onto the bus. The memory device stores the code in a programmable register on the memory device. In this preferred embodiment, the first amount of data corresponding to the first block size information is output after the number of clock cycles of the external clock transpire.

Claims

1. A method of controlling a synchronous memory device, wherein the memory device includes a plurality of memory cells, the method of controlling the memory device comprises:

providing first block size information to the memory device, wherein the first block size information defines a first amount of data to be output by the memory device onto a bus in response to a read request; and

issuing a first read request to the memory device, wherein in response to the first read request, the memory device outputs the first amount of data corresponding to the first block size information onto the bus synchronously with respect to an external clock signal.

2. The method of claim 1 wherein first block size information further defines a first amount of data to be input by the memory device from the bus in response to a write request, the method further including issuing a first write request to the memory device wherein, in response to the first write request, the memory device inputs the first amount of data corresponding to the first block size information from the bus synchronously with respect to the external clock signal.

3. The method of claim 2 further including:

providing second block size information to the memory device, wherein the second block size information defines a second amount of data to be input by the memory device from the bus in response to a write request; and

issuing the second write request to the memory device, wherein in response to the second write request, the memory device inputs the amount of data corresponding to the second block size information from the bus synchronously with respect to the external clock signal.

4. The method of claim 2 wherein the first block size information and the first write request are included in a request packet.

5. The method of claim 4 wherein the first block size information and the first write request are included in the same request packet.

6. The method of claim 1 further including issuing a second read request to the memory device, wherein in response to the second read request, the memory device outputs the first amount of data corresponding to the first block size information onto the bus synchronously with respect to the external clock signal.

7. The method of claim 6 further including:

providing second block size information to the memory device, wherein the second block size information defines a second amount of data to be output onto the bus in response to a read request; and

issuing a third request to the memory device, wherein in response to the third read request, the memory device outputs the second amount of data corresponding to the second block size information onto the bus synchronously with respect to the external clock signal.

8. The method of claim 1 further including providing a code which is representative of a delay time to transpire before data is output onto the bus after receipt of a read request, wherein the memory device stores the code in an access time register on the memory device.

9. The method of claim 8 further including receiving the external clock signal wherein the first amount of data corresponding to the first block size information is output in accordance with the delay time.

10. The method of claim 8 wherein the code represents a number of cycles of the external clock and wherein the number of cycles is a fraction or a whole number.

11. The method of claim 1 wherein the first block size information and the first read request are included in a request packet.

12. The method of claim 11 wherein the first block size information and the first read request are included in the same request packet.

13. The method of claim 11 wherein the first block size information is a binary representation of the amount of data to be output after receipt of the first read request.

14. The method of claim 11 wherein the first block size information is indicative of an amount of data corresponding to a page mode access.

15. The method of claim 11 wherein the external clock signal has a fixed frequency and wherein the first amount of data corresponding to the first block size information is output synchronously during a plurality of clock cycles of the external clock signal.

16. The method of claim 11 further including generating at least one internal clock signal using the external clock signal wherein the first amount of data corresponding to the first block size information is output onto the bus synchronously with respect to at least one internal clock signal.

17. The method of claim 16 wherein the internal clock signal is generated by a delay locked loop.

18. A method of operation of a synchronous memory device, wherein the memory device includes a plurality of memory cells, the method of operation of the memory device comprises:

receiving an external clock signal;

receiving first block size information from a bus controller, wherein the first block size information defines a first amount of data to be output by the memory device onto a bus in response to a read request;

receiving a first request from the bus controller; and

outputting the first amount of data corresponding to the first block size information, in response to the first read request, onto the bus synchronously with respect to the external clock signal.

19. The method of claim 18 further including:

receiving a second read request from the bus controller, and

outputting the first amount of data corresponding to the first block size information, in response to the second read request, onto the bus synchronously with respect to the external clock signal.

20. The method of claim 18 wherein first block size information further defines a first amount of data to be input by the memory device from the bus in response to a write request, the method further including:

receiving a first write request from the bus controller, and

inputting the first amount of data corresponding to the first block size information, in response to the first write request, from the bus synchronously with respect to the external clock signal.

21. The method of claim 20 further including:

receiving second block size information, wherein the second block size information defines a second amount of data to be input from the bus in response to a write request; and

receiving the second write request from the bus controller;

inputting the amount of data corresponding to the second block size information, in response to the second write request, from the bus synchronously with respect to the external clock signal.

22. The method of claim 20 wherein the first block size information and the first write request are included in a request packet.

23. The method of claim 22 wherein the first block size information and the first write request are included in the same request packet.

24. The method of claim 18 further including storing a delay time code in an access time register, the delay time code being representative of a number of clock cycles to transpire before data is output onto the bus after receipt of a read request and wherein the first amount of data corresponding to the first block size information is output in accordance with the delay time code.

25. The method of claim 24 wherein the delay time code is stored in the access time register after power is applied to the memory device.

26. The method of claim 25 wherein the number of clock cycles is a fraction or a whole number.

27. The method of claim 18 wherein the first block size information and the first read request are included in a request packet.

28. The method of claim 27 wherein the first block size information and the first read request are included in the same request packet.

29. The method of claim 18 wherein the first block size information is a binary representation of the first amount of data to be output after receipt of the first read request.

30. The method of claim 18 wherein the first block size information is indicative of an amount of data corresponding to one of a plurality of page mode accesses.

31. The method of claim 18 wherein the external clock signal has a fixed frequency and wherein the first amount of data corresponding to the first block size information is output synchronously during a plurality of clock cycles of the external clock signal.

32. The method of claim 31 further including automatically precharging the synchronous memory device after executing the first read request.

33. The method of claim 18 further including generating at least one internal clock signal using a delay locked loop and the external clock signal wherein the first amount of data corresponding to the first block size information is output onto the bus synchronously with respect to at least one internal clock signal.

35. The method of claim 32 wherein the value is hard wired.

36. The method of claim 32 wherein the block size information and the first read request are included in the same request.

37. The method of claim 32 further including:

receiving a second read request from the bus controller wherein the block size information and the second read request are included in the same request;

outputting the first amount of data corresponding to the block size information onto the bus in response to the second read request; and

wherein the memory device outputs the data synchronously with respect to the external clock signal, during a plurality of clock cycles of the external clock signal and in accordance with the valued stored in the time delay register.

38. The method of claim 32 wherein the value represents a fraction or whole number of clock cycles of the external clock signal.

34. A method of operation of a synchronous memory device, wherein the memory device includes a plurality of memory cells and a time delay register, the method of operation of the memory device comprises:

storing a value in the time delay register, the value being representative of a number of external clock cycles to transpire after which the memory device responds to a read request;

receiving an external clock signal wherein the external clock signal has a fixed frequency;

receiving block size information from a bus controller, wherein the block size information defines a first amount of data to be output by the memory device onto the bus in response to a read request;

receiving a first read request from the bus controller;

outputting the first amount of data corresponding to the block size information onto the bus in response to the first read request,

wherein the memory device outputs the data synchronously with respect to the external clock signal, during a plurality of clock cycles of the external clock signal and in accordance with the value stored in the time delay register.