Multi-stream associative memory architecture for computer telephony
First Claim
Patent Images
1. A communications circuit comprising:
- a first content-addressable memory block having;
an address input,a plurality of physical locations each of which comprises an address field responsive to the address input and an output field, andan output responsive to the output fields,a second content-addressable memory block having;
an address input,a plurality of physical locations each of which comprises an address field responsive to the address input, and an output field, andan output responsive to the output fields, anda first data memory having an address input responsive to the output of the first content addressable memory block and to the output of the second content-addressable memory block, anda time division multiplexed communications interface circuitry operatively connected to the content-addressable memory blocks for switching time division multiplexed time slot data from a first plurality of data streams onto a second plurality of data streams using the content-addressable memory blocks,wherein the first content-addressable memory block and the second content-addressable memory blocks are constructed and arranged to substantially simultaneously receive and process a same input address.
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Abstract
Aspects of the present invention are directed to communications circuits and method that utilize associative memories for providing telephony switching of data between different time slots in one or more time division multiplexed (TDM) serial data lines or streams. The communications circuit may include a first content-addressable memory block and a second content-addressable memory block each of which receive the same address for independently generating tags for accessing a data memory to provide data to or receive data from TDM data lines.
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Citations
16 Claims
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1. A communications circuit comprising:
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a first content-addressable memory block having; an address input, a plurality of physical locations each of which comprises an address field responsive to the address input and an output field, and an output responsive to the output fields, a second content-addressable memory block having; an address input, a plurality of physical locations each of which comprises an address field responsive to the address input, and an output field, and an output responsive to the output fields, and a first data memory having an address input responsive to the output of the first content addressable memory block and to the output of the second content-addressable memory block, and a time division multiplexed communications interface circuitry operatively connected to the content-addressable memory blocks for switching time division multiplexed time slot data from a first plurality of data streams onto a second plurality of data streams using the content-addressable memory blocks, wherein the first content-addressable memory block and the second content-addressable memory blocks are constructed and arranged to substantially simultaneously receive and process a same input address. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A communications circuit comprising:
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a first content-addressable memory block having; an address input, a plurality of physical locations each of which comprises an address field responsive to the address input and an output field, and an output responsive to the output fields, a second content-addressable memory block having; an address input, a plurality of physical locations each of which comprises an address field responsive to the address input and an output field, and an output responsive to the output fields, a first data memory having an address input responsive to the output of content-addressable memory block and to the output of the second content-addressable memory block, and time division multiplexed communications interface circuitry operatively connected to the content-addressable memory blocks for switching time division multiplexed time slot data from a first plurality of data streams onto a second plurality of data streams using the content-addressable memory blocks. - View Dependent Claims (8, 9)
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10. A communications circuit, comprising:
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means for providing a first address to a first address input of a first content-addressable memory block; means for retrieving a first tag corresponding to the first address in the first content-addressable memory block; means for accessing a first data item in a first data memory at a first location pointed to by the first tag; means for providing the first address to a second address input of a second content-addressable memory block; means for retrieving a second tag corresponding to the first address in the second content-addressable memory block, and means for accessing a second data item in the first data memory at a second location pointed to by the second tag; and time division multiplexed communications interface means operatively connected to the content-addressable memory blocks for switching time division multiplexed time slot data from a first plurality of data streams onto a second plurality of data streams using the content addressable memory blocks; wherein the communications system is constructed and arranged such that the first address is substantially simultaneously provided to the first address input and the second address input. - View Dependent Claims (11, 12)
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13. A communication method, comprising:
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simultaneously providing a first address to a first address input of a first content addressable memory block and providing a first address to a second address input of a second content-addressable memory block, retrieving a first tag corresponding to the first address in response to the step of providing the first address to a first address input of a first content addressable memory block, retrieving a second tag corresponding to the second address in response to the step of providing a first address to a second address input of a second content-addressable memory block, accessing a first data item in a data memory at a first location pointed to by the first tag, and accessing a second data item in the data memory at a second location pointed to by the second tag; and switching time division multiplexed time slot data from a first plurality of data streams onto a second plurality of data streams using the content-addressable memory blocks. - View Dependent Claims (14, 15, 16)
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Specification