Digital super-regenerative detector RF receiver
First Claim
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1. A receiver for receiving a digitally coded radio-frequency signal from a transmitter, comprising:
- an RF detector for detecting the digitally coded radio-frequency signal and for generating a digital signal responsive to the digitally coded radio-frequency signal, the RF detector comprising an analog amplifier coupled to an analog oscillator for generating an analog oscillator signal and a digital signal generator responsive to the analog oscillator signal for producing the digital signal;
a clock signal generator for producing a clock signal;
a delayed clock signal generator for generating a first offset clock signal and a second offset clock signal in response to the clock signal; and
a first comparator for comparing the second offset clock signal with the digital signal and producing a combination clocked and analog bias signal and supplying the combination clocked and analog bias signal to the oscillator to stabilize the oscillator timing;
a second comparator for comparing the first offset signal with the digital signal and generating a detected code signal in response thereto.
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Abstract
A digital super-regenerative receiver is provided having an analog RF detector and a regenerative oscillator. The output of the RF detector is used to generate a digital signal from which the oscillator bias is adjusted, in order to maintain the oscillator start-up time at a fixed level. The circuit senses if the start-up time is earlier or later than the predetermined start-up time and produces an output when the majority of the start times are ahead of the expected start time.
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2 Claims
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1. A receiver for receiving a digitally coded radio-frequency signal from a transmitter, comprising:
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an RF detector for detecting the digitally coded radio-frequency signal and for generating a digital signal responsive to the digitally coded radio-frequency signal, the RF detector comprising an analog amplifier coupled to an analog oscillator for generating an analog oscillator signal and a digital signal generator responsive to the analog oscillator signal for producing the digital signal; a clock signal generator for producing a clock signal; a delayed clock signal generator for generating a first offset clock signal and a second offset clock signal in response to the clock signal; and a first comparator for comparing the second offset clock signal with the digital signal and producing a combination clocked and analog bias signal and supplying the combination clocked and analog bias signal to the oscillator to stabilize the oscillator timing; a second comparator for comparing the first offset signal with the digital signal and generating a detected code signal in response thereto. - View Dependent Claims (2)
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Specification
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Current AssigneeThe Chamberlain Group, Inc. (The Chamberlain Group LLC)
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Original AssigneeThe Chamberlain Group, Inc. (The Chamberlain Group LLC)
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InventorsSchleifer, Fred Freybler
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Primary Examiner(s)Vo, Don N.
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Application NumberUS08/956,501Time in Patent Office867 DaysField of Search375/271, 375/316, 375/318, 375/322, 375/324, 375/328, 375/344, 329/315, 329/324, 329/341, 329/343, 329/344, 340/825.72, 455/182.1, 455/182.2, 455/192.1, 455/192.2, 455/226.1, 455/255, 455/257, 455/265, 318/264, 318/265, 318/266, 49/28US Class Current375/318CPC Class CodesH03D 11/00 Super-regenerative demodula...H03D 11/08 by means of semiconductor d...H04B 1/30 for homodyne or synchrodyne...
