Method and system for maintaining hierarchy throughout the integrated circuit design process

• US 6,035,106 A
• Filed: 04/28/1997
• Issued: 03/07/2000
• Est. Priority Date: 04/28/1997
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Carruthers, Colin, Buchanan, Irene
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): DO, THUAN V
• Application Number:
  US08/840,338
• Time in Patent Office: 1,044 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491
• US Class Current: 703/1
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A method and system for translating abstract structural or behavioral circuit descriptions to physically implementable files, preferably suitable for use in a Field Programmable Gate Array (FPGA) or other programmable device. A selection of layouts are generated for a cell definition (a function), allowing optimization and acceleration of circuit placement and routing without compromising design hierarchy or altering design function. Layout transformation functions may be manually initiated or automatically selected and applied during implementation of a placement algorithm.

Claims

1. For configuring a logic array integrated circuit having a plurality of function blocks to implement a logic design, the logic design comprising a plurality of interconnected logic cells, each occurrence of a logic cell in the design being an instance of the logic cell, each of said logic cells being defined by a functional definition common to all instances of said logic cell, and each of said defined logic cells having a default physical layout, a method of using a computer to place said logic design in said logic array while at least partially maintaining a hierarchical relationship among logic cell instances and a logic cell functional definition, said method comprising the steps of:

generating a first alternative physical layout of a first logic cell, said first alternative layout having a functional definition identical to that of said default layout of said first logic cell;

determining whether said first alternative layout is preferable to said default layout of said first logic cell when one or more instances of said first logic cell is placed;

selecting either of said first alternative layout and said default layout for placement in at least one of said function blocks;

placing said plurality of logic cells, including said first logic cell having said selected layout, among said function blocks, thereby allowing selective placement of the logic design while at least partially maintaining the hierarchical relationship among the plurality of logic cell instances and the logic cell functional definition.

2. The method of claim 1 wherein said function blocks are contained within a programmable integrated circuit.

3. The method of claim 2 wherein said programmable integrated circuit is a field programmable gate array.

4. The method of claim 1 wherein said determining step comprises assessing the effect of substituting said alternative layout for said default layout in said design.

5. The method of claim 4 wherein said effect assessing step comprises ascertaining the amount of interconnecting wire between function blocks required by said alternative layout.

6. The method of claim 1 wherein said first alternative layout is an n-degree rotation of the default layout of said first logic cell about a central axis, where n is between 1 and 360.

7. The method of claim 1 wherein said first alternative layout is a reflection of the default layout of said first logic cell about a line set at an n-degree angle from vertical, where n is between 0 and 180.

8. The method of claim 1 wherein said first alternative layout is generated in response to transformation instructions chosen by a circuit designer.

9. The method of claim 1 wherein said first alternative layout is generated in response to an automatically selected transformation function, selected from a plurality of available transformation functions.

10. The method of claim 9 wherein said automatically selected transformation function is selected from said plurality of functions in a manner which optimizes the length of connecting wires between said first logic cell and another logic cell connected to said first logic cell when said design is placed among said function blocks.

11. The method of claim 1 wherein said design further comprises the step of routing connections between said logic cells.

12. A method of placing a logic design among function blocks in a configurable logic device, said logic design comprising a plurality of interconnected logic cells, each of said logic cells being defined by a functional definition, each of said logic cells having a default physical layout, and said logic cells being hierarchically related to each other within said logic design such that all instances of a logic cell have an identical functional definition, said method comprising the steps of:

calculating a plurality of alternative layouts for each of said logic cells;

preliminarily placing each of said logic cells among said function blocks;

substituting a first alternative layout for a default layout of a first logic cell;

checking the compatibility of said substitution with said logic device;

calculating the cost of implementing said substitution;

retaining said substitution if said cost is lower than the cost of implementing said default layout.