Manufacturing method and apparatus of a semiconductor integrated circuit device

• US 6,035,111 A
• Filed: 11/13/1996
• Issued: 03/07/2000
• Est. Priority Date: 09/22/1992
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited, Fujitsu VLSI Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited, Fujitsu VLSI Limited (Fujitsu Limited)
• Inventors: Shimazaki, Takeshi, Uchida, Yoshitaka, Kamiya, Yoshihiro, Saida, Kiyoshi, Tsuyuki, Teruhisa, Nishiwaki, Yukimi, Murakami, Takako, Kawazoe, Kazunori, Fujine, Eiji, Suzuki, Rieko, Itazu, Kazushige
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Siek, Vuthe
• Application Number:
  US08/748,534
• Time in Patent Office: 1,210 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/578, 395/500
• US Class Current: 716/113
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits

Abstract

According to the present invention, using a computer aided design system for designing semiconductor integrated circuits wherein a plurality of logic cells forming a circuit net are disposed on a semiconductor chip according to a net list specifying a connection pattern assigned among input and output terminals of a plurality of logic cells and a wiring length connecting the terminals.

Claims

1. An apparatus for manufacturing a semiconductor integrated circuit device comprising:

a data input means for generating a general wiring net data for connection of a plurality of input and output terminals of a plurality of logic cells and for generating delay time data relating to signals from the output terminals to the input terminals, said general wiring net data comprising a first wiring net data for connecting the plurality of output terminals to at least one of the input terminals and a second wiring net data for connecting a single output terminal to the plurality of input terminals, said first wiring net data being combined with said delay time data for generating a first simulation design model, said first wiring net data being used for generating a second simulation design model, and said second wiring net data being used for generating a third simulation design model;

a first determining means for distinguishing which one of said first and second wiring net data is input from said data input means;

a selecting means for selecting one of said simulation design models in accordance with a determination of said first determining means;

a first model generating means for generating said first simulation design model based on said first wiring net data and said delay time data when said selecting means selects said first simulation design model;

a second model generating means for generating said second simulation design model based on said first wiring net data when said selecting means selects said second simulation design model; and

a third model generating means for generating said third simulation model based on said second wiring net data when said first determining means determines that said wiring net data is said second wiring net data.

2. An apparatus for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said first model generating means comprises:

an intermediate gate generating means for generating an intermediate gate between said output terminals and input terminals of said plurality of logic cells, said intermediate gate having the same number of gate input terminals as said output terminals of said logic cells and having the same number of gate output terminals as said input terminals of said logic cells; and

wherein said delay time data from said output terminals to input terminals of said logic cells is set between said gate input terminals and gate output terminals.

3. An apparatus for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said second model generating means comprises:

an intermediate gate generating means for generating the same number of intermediate gates as the input terminals of said logic cells, each intermediate gate having a single gate output terminal and the same number of gate input terminals as said output terminals of said logic cells; and

wherein said delay time data from said output terminals and input terminals of said logic cells is set for said gate input terminals and gate output terminals of said intermediate gates.

4. An apparatus for manufacturing a semiconductor integrated circuit according to claim 1, wherein said third model generating means comprises:

an intermediate gate generating means for generating an intermediate gate, said intermediate gate having the same number of gate output terminals as said input terminals of said logic cells and the same number of gate input terminals as the output terminals of at least one of said logic cells; and

wherein said gate output terminals set delay time data between said output terminals of at least one of said logic cells and said input terminals of said logic cells.

5. A method for disposing a plurality of logic cells included in a semiconductor integrated circuit device on a semiconductor chip based on a net wiring list including a plurality of wiring nets for connecting output terminals and input terminals of said logic cells to each other, the method comprising the steps of:

setting a wiring length between any pair of said terminals among said input and output terminals within a specific wiring net to a predetermined wiring length;

providing a bypass route having a specified length between said pair of terminals when the actual wiring length between said pair of terminals is less than said predetermined wiring length, the length of said bypass route corresponding to said predetermined wiring length;

disposing a dummy cell in said bypass route, said dummy cell having intermediate terminals connected with said pair of terminals; and

disposing the plurality of logic cells including said dummy cell, onto said semiconductor chip in accordance with said predetermined wiring length.

6. The method according to claim 5, further comprising the steps of:

defining predetermined allocate regions for the plurality of logic cells;

computing the distance between the predetermined allocate regions and each of the plurality of logic cells; and

limiting allocating each of the plurality logic cells to each of the predetermined allocate regions in accordance with the computation results.

7. The method according to claim 6, further comprising the step of determining whether each of the plurality of logic cells includes a definite coordinate value prior to the computing step, wherein the computing step includes computing the distance between the definite coordinate value and each of the predetermined allocate regions.

8. The method according to claim 5, further comprising the step of resetting a wiring length to a predetermined wiring length in the logic cells associated with at least one logic cell previously placed on the semiconductor integrated circuit.

9. The method according to claim 5, further comprising the step of updating the net wiring list when the dummy cell is disposed.