Fir filter architecture

• US 6,035,320 A
• Filed: 01/04/1995
• Issued: 03/07/2000
• Est. Priority Date: 01/04/1995
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Krenik, William R., Kiriaki, Sami
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US08/368,679
• Time in Patent Office: 1,889 Days
• Field of Search: 364/825, 364/602, 364/724.16, 364/724.13
• US Class Current: 708/819
• CPC Class Codes: H03H 17/06 Non-recursive filters

Abstract

A novel Finite Impulse Response filter (FIR) Filter is provided which includes a plurality of multipliers (14-22), a plurality of multiplexers (24-32), and a plurality of sample and hold circuits (34-42). At least two of the sample and hold circuit output signals (1-5) may be multiplexed in a round robin fashion to at least two of the multipliers (14-22). The multipliers may receive as a second input, fixed tap coefficient signals (C₁ -C₅) for multiplication with the multiplexed sample and hold circuit output signals (1-5).

Claims

1. An FIR filter having an input signal and a filtered output, comprising:

a plurality of multipliers, each said multiplier including a first multiplier input, a second multiplier input and an output, each said first multiplier input receiving a signal representing an FIR coefficient;

a plurality of sample and hold circuits, each of said plurality of sample and hold circuits including a first output and operable to sample said input signal and hold the value of said input signal on said first output for a predetermined time;

a plurality of multiplexers, each comprising a plurality of multiplexer inputs and a second output, at least two of said second outputs each coupled to one of said second multiplier inputs, and at least one of said plurality of multiplexer inputs of a first predetermined number of multiplexers coupled to said first output of a first of said sample and hold circuits; and

a summer connected to said output of each of said multipliers, said summer having an output which is said filtered output of said FIR filter.

2. The FIR filter of claim 1, further comprising:

a coefficient register comprising a plurality of coefficient outputs and operable to store a plurality of data values representing FIR coefficients, said coefficient register further operable to produce a coefficient signal on at least two of said plurality of coefficient outputs representing an FIR coefficient, wherein at least one of said coefficient outputs is coupled to one of said first multiplier inputs.

3. The FIR filter of claim 2, wherein said coefficient register is further operable to receive said plurality of data values as inputs.

4. The FIR filter of claim 1 wherein each said coefficient signal comprises a digital value.

5. The FIR filter of claim 4 wherein each of said plurality of multipliers further comprises conversion circuitry operable to convert a digital value at said first multiplier input into an analog signal.

6. The FIR filter of claim 1 wherein the number of said plurality of multipliers equals the number of said plurality multiplexers.

7. The FIR filter of claim 1 wherein each said second output comprises an analog signal.

8. The FIR filter of claim 1 wherein the number of said plurality of sample and hold circuits equals the number of said plurality of inputs on each of said multiplexers.

9. The FIR filter of claim 1 wherein each said first output comprises an analog signal.

10. The FIR filter of claim 1, further comprising:

a plurality of coefficient circuits each comprising a coefficient output, said coefficient circuits operable to produce a coefficient signal at said coefficient output representing an FIR coefficient, wherein at least one coefficient output is coupled to one of said first multiplier inputs.

11. A method of making an FIR filter which has an input signal and a filtered output, said method comprising the steps of:

supplying a plurality of fixed tap coefficient signals to a plurality of multipliers, one fixed tap coefficient signal per multiplier;

providing said input signal to each of a plurality of sample and hold circuits, each of said sample and hold circuits having an output which provides an output signal;

multiplexing said plurality of sample and hold circuit output signals in a round robin manner to at least two of said multipliers; and

summing the output of each of said plurality of multipliers, said sum being the filtered output of said FIR filter.

12. The method of claim 11, further comprising the step of sampling an input signal with each said sample and hold circuit in a round robin manner.

13. The method of claim 11 wherein said fixed tap coefficient signals are digital signals.

14. The method of claim 11 wherein said sample and hold circuit output signals are analog signals.

15. The method of claim 11 wherein said plurality of fixed tap coefficient signals is supplied by an FIR coefficient register.

16. The method of claim 11 wherein said multiplexing step further comprises the step of multiplexing said output signals in a round robin manner to each said multiplier.

17. A method of making an FIR filter which has an input signal and a filtered output, said method comprising the steps of:

providing said input signal to each of a plurality of sample and hold circuits, each of said sample and hold circuits having an output which provides an output signal;

supplying said plurality of sample and hold circuit output signals to a plurality of multipliers, one output signal per multiplier;

multiplexing a plurality of fixed tap coefficient signals in a round robin manner to each of said plurality of multipliers wherein said fixed tap coefficient signals are analog signals; and

summing the output of each of said plurality of multipliers, said sum being the filtered output of said FIR filter.

18. The method of claim 17 wherein each of said plurality of fixed tap coefficient signals is supplied by a digital to analog converter.

19. The method of claim 18 wherein each said digital to analog converter receives a digital input from an FIR coefficient register.

20. The method of claim 17 wherein said sample and hold circuit output signals are analog signals.