Dual clocked synchronous memory device having a delay time register and method of operating same

• US 6,035,365 A
• Filed: 11/27/1998
• Issued: 03/07/2000
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US09/200,446
• Time in Patent Office: 466 Days
• Field of Search: 365/230.03, 710/130, 710/129, 710/104, 710/126, 711/167, 713/401
• US Class Current: 710/305
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A synchronous memory device having at least one memory section which includes a plurality of memory cells. The memory device comprises a register to store a value which is representative of a delay time after which the memory device responds to a read request and clock receiver circuitry to receive first and second external clock signals. The memory device also includes an output driver(s) to output data on a bus, in response to a read request and in accordance with the delay time, wherein a first portion of the data is output synchronously with respect to the first external clock signal and a second portion of the data is output synchronously with respect to the second external clock signal. The memory device may include a delay locked loop to generate internal clock signal(s) using the external clock signal(s). The output drivers output data on the bus in response to the internal clock signal(s). The memory device may include input receiver circuitry, coupled to the bus, the receive the read request, wherein the read request is sampled from the bus synchronously with respect to the first external clock signal.

Claims

1. A synchronous memory device having at least one memory section which includes a plurality of memory cells, the memory device comprises:

a register to store a value which is representative of a delay time after which the memory device responds to a read request;

clock receiver circuitry to receive first and second external clock signals; and

an output driver to output data on a bus in response to a read request and in accordance with the delay time wherein a first portion of the data is output synchronously with respect to the first external clock signal and a second portion of the data is output synchronously with respect to the second external clock signal.

2. The semiconductor device of claim 1 further including internal clock generation circuitry, coupled to the clock receiver circuitry, to generate a first internal clock signal using at least the first external clock signal wherein, in response to the first internal clock signal, the output driver outputs data.

3. The memory device of claim 2 wherein the internal clock generation circuitry includes a delay locked loop to generate the first internal clock signal.

4. The memory device of claim 1 further including a delay locked loop to generate a first internal clock signal using the first and second external clock signals wherein, in response to the first internal clock signal, the output driver outputs data.

5. The memory device of claim 4 wherein the first and the second external clock signals are complementary.

6. The memory device of claim 1 further including a first delay locked loop to generate a first internal clock signal and a second delay locked loop to generate a second internal clock signal wherein, in response to the first and second internal clock signals, the output driver outputs data.

7. The memory device of claim 6 wherein the first and the second internal clock signals are complementary.

8. The memory device of claim 6 wherein the first delay locked loop generates the first internal clock signal using the first and the second external clock signals.

9. The memory device of claim 6 further including a multiplexer coupled to the delay locked loop to receive the first and the second internal clock signals, the multiplexer includes a first input coupled to a first internal I/O line and a second input coupled to a second internal I/O line, wherein the multiplexer couples the first internal I/O line to an input of the output driver in response to the first internal clock signal and couples the second internal I/O line to the input of the output driver in response to the second internal clock signal.

10. The memory device of claim 9 wherein the output driver is a transistor including a first electrode coupled to an external bus, a second electrode coupled to a first potential, and a gate coupled to the output of the multiplexer, the transistor being switched on and off in response to the output of the multiplexer.

11. The memory device of claim 6 wherein the output driver outputs data in response to a rising edge of the first internal clock signal and in response to a rising edge of the second internal clock signal.

12. The memory device of claim 1 wherein the delay time is a fraction or a whole number of clock cycles of the first external clock signal.

13. The memory device of claim 1 further including input receiver circuitry, coupled to the bus, to receive the read request, wherein the read request is sampled from the bus synchronously with respect to the first external clock signal.

14. The memory device of claim 13 wherein the input receiver circuitry includes a first input latch coupled to the bus, wherein the first input latch samples a first information bit synchronously with respect to a rising edge of the first external clock signal.

15. The memory device of claim 14 wherein the input receiver circuitry includes a second input latch coupled to the bus, wherein the second input latch samples a second information bit synchronously with respect to a rising edge of the second external clock signal.

16. The memory device of claim 15 the first and second information bits include address and control information.

17. The memory device of claim 14 wherein the input receiver circuitry further includes a second input latch coupled to the bus, wherein the second input latch samples a second information bit synchronously with respect to a falling edge of the first external clock signal.

18. The memory device of claim 17 the first and second information bits include address and control information.

19. The memory device of claim 13 wherein the read request includes N bits of information and the bus includes M number of signal lines wherein M is substantially less than N.

20. The memory device of claim 1 wherein the first and second external clock signals have a fixed frequency.

21. The memory device of claim 1 wherein the value which is representative of the delay time is stored in the register after power is applied to the memory device.

22. An integrated circuit device having at least one memory section which includes a plurality of memory cells, the integrated circuit device comprises:

a register to store a value which is representative of a number of cycles of a first external clock signal to transpire after which the memory device responds to a read request; and

a plurality of output drivers, each output driver being coupled to an external bus to output data on the external bus after the number of cycles of the first external clock signal have transpired, wherein a first portion of the data is output synchronously with respect to the first external clock signal and a second portion of the data is output synchronously with respect to a second external clock signal.

23. The integrated circuit device of claim 22 further including a delay locked loop to generate a first internal clock signal wherein a plurality of output drivers output data on the bus in response to the first internal clock signal.

24. The integrated circuit device of claim 23 wherein the delay locked loop generates the first internal clock signal using the first external clock signal.

25. The integrated circuit device of claim 23 wherein the delay locked loop generates the first internal clock signal using the first and second external clock signals.

26. The integrated circuit device of claim 22 further including internal clock generation circuitry to generate first and second internal clock signals wherein the output drivers output data on the bus in response to the first and the second internal clock signal.

27. The integrated circuit device of claim 26 wherein the internal clock generation circuitry includes a delay locked loop to generate the first internal clock signal using the first and the second external clock signals.

28. The integrated circuit device of claim 26 wherein the internal clock generation circuitry includes a first delay locked loop to generate the first internal clock signal and a second delay locked loop to generate the second internal clock signal.

29. The integrated circuit device of claim 28 wherein the first delay locked loop generates the first internal clock signal using the first and second external clock signals.

30. The integrated circuit device of claim 28 wherein the first delay locked loop generates the first internal clock signal using the first and the second external clock signals and the second delay locked loop generates the second internal clock signal using the first and the second external clock signals.

31. The integrated circuit device of claim 26 wherein the plurality of output drivers output data on the bus in response to a rising edge of the first internal clock signal and in response to a rising edge of the second internal clock signal.

32. The integrated circuit device of claim 26 wherein the plurality of output drivers include a first output driver and a second output driver and wherein the integrated circuit device further includes:

a first multiplexer coupled to a first output driver;

a second multiplexer coupled to a second output driver;

wherein the first multiplexer couples a first internal I/O line to the first output driver in response to the first internal clock signal and couples a second internal I/O line to the first output driver in response to the second internal clock signal; and

wherein the second multiplexer couples a third internal I/O line to the second output driver in response to the first internal clock signal and couples a fourth internal I/O line to the second output driver in response to the second internal clock signal.

33. The integrated circuit device of claim 22 wherein the number of cycles of the first external clock signal is a fraction or a whole number of clock cycles.

34. The integrated circuit device of claim 22 wherein the output drivers output the first portion of the data in response to a rising edge of the first external clock and output the second portion of the data in response to a rising edge of the second external clock signal.

35. The integrated circuit device of claim 22 further including input receiver circuitry, coupled to the bus, to receive a read request, wherein the read request is sampled from the bus synchronously with respect to the first external clock signal.

36. The integrated circuit device of claim 35 wherein the input receiver circuitry includes a first input latch coupled to the bus, wherein the first input latch samples a first information bit synchronously with respect to a rising edge of the first external clock signal.

37. The integrated circuit device of claim 36 wherein the input receiver circuitry includes a second input latch coupled to the bus, wherein the second input latch samples a second information bit synchronously with respect to a rising edge of the second external clock signal.

38. The integrated circuit device of claim 37 the first and second information bits include address and control information.

39. The integrated circuit device of claim 36 wherein the input receiver circuitry further includes a second input latch coupled to the bus, wherein the second input latch samples a second information bit synchronously with respect to a falling edge of the first external clock signal.

40. The integrated circuit device of claim 39 the first and second information bits include address and control information.

41. The integrated circuit device of claim 35 wherein the read request includes N bits of information and the bus includes M number of signal lines wherein M is substantially less than N.

42. The integrated circuit device of claim 22 wherein the first and second external clock signals have a fixed frequency.

43. The integrated circuit device of claim 22 wherein the value which is representative of the delay time is hardwired.

44. A method of operating a synchronous semiconductor memory device having a register for storing a value which is representative of a time delay after which the memory device responds to a read request and at least one memory section including a plurality of memory cells, the method comprising:

issuing a read request to the memory device wherein the memory device, in response to the read request, outputs a first portion of the data on a bus in accordance with the time delay and synchronously with respect to a first external clock signal and outputs a second portion of the data, after the first portion of the data, synchronously with respect to a second external clock signal;

receiving the first portion of data from the memory device synchronously with respect to the first external clock signal; and

receiving a second portion of data from the memory device synchronously with respect to a second external clock signals.

45. The method of claim 44 wherein the read request and information indicative of the value are provided to the memory device in a single request packet.

46. The method of claim 44 further including the steps of:

initializing the register in the memory device by issuing a set register request on the bus; and

providing the value which is representative of the time delay to the memory device.

47. The method of claim 44 wherein the time delay is a fraction or a whole number of clock cycles of the first external clock signal.

48. The method of claim 44 further including issuing a set register request, wherein, in response to the set register request, the memory device stores the value in the register.

49. The method of claim 44 further including the steps of:

identifying the memory device on the bus using a device identification code;

initializing the register in the memory device by issuing a set register request on the bus; and

providing the value which is representative of the time delay to the memory device.

50. The method of claim 49 wherein the device identification code, the set register request, and information identifying the time delay after which the memory device responds to a read request are provided to the memory device in a signal request packet.

51. The method of claim 49 wherein the device identification code is a unique device code.

52. The method of claim 49 wherein the device identification code identifies the memory device and at least one other memory device coupled to the bus.