Integrated circuit

• US 6,035,380 A
• Filed: 02/19/1998
• Issued: 03/07/2000
• Est. Priority Date: 02/14/1995
• Status: Expired due to Fees

• Current Assignee: Christopher D. Shelton, David Chaum, Marius P.M. Schilder, Martin S. Kelly, Niels T. Ferguson, Reinhard Posch, Volker Schindler, William E. Orme, Wolfgang Mayerwieser
• Original Assignee: Christopher D. Shelton, David Chaum, Marius P.M. Schilder, Martin S. Kelly, Niels T. Ferguson, Reinhard Posch, Volker Schindler, William E. Orme, Wolfgang Mayerwieser
• Inventors: Ferguson, Niels T., Chaum, David, Schindler, Volker, Shelton, Christopher D., Orme, William E., Kelly, Martin S., Posch, Reinhard, Schilder, Marius P. M., Mayerwieser, Wolfgang
• Primary Examiner(s): Pan, Daniel H.
• Application Number:
  US08/875,936
• Time in Patent Office: 747 Days
• Field of Search: 380/4, 380/49, 235/379, 235/481, 235/380, 235/492, 713/200, 711/163, 711/155.2, 711/206, 711/152, 711/151, 371/57.2, 707/9, 714/6, 714/764, 712/227, 712/244, 712/235
• US Class Current: 711/163
• CPC Class Codes: G06K 19/073 Special arrangements for circuits, e.g. for protecting identification code in memory protection against unauthorised use of computer memory G06F12/14
• CPC Class Codes: G06Q 20/341 Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
• CPC Class Codes: G06Q 20/3576 Multiple memory zones on card
• CPC Class Codes: G07F 7/1008 Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system

Abstract

A single chip processor for use in a smart card has a plurality of instruction memory areas and a processor. Different instructions sets are selectively executable in response to a signal defining a memory area from which instructions are supplied. Preferably instruction and data memory areas are addressable as pages, wherein a page address cannot be directly accessed by a subset of instructions. The processor may include a central processing unit and a cryptographic logic unit which operate at different times and share common instruction memory and sequencing logic. Instructions are supplied to said cryptographic logic unit at an integer multiple of the rate at which they are supplied to said central processing unit.

Claims

1. A single chip integrated circuit comprising an integrated circuit on a single chip having processing means arranged to process instructions supplied from storage means, characterized in that

said storage means comprises a first storage region and a second storage region;

first instructions are selectively supplied to said processing means from said first storage region and said second region; and

enabling means are arranged to

enable said processing means to be responsive to privileged instructions if said first instructions are received from said first storage region, and

to disable said processing means from being responsive to said privileged instructions if said first instructions are received from said second storage region.

2. A circuit according to claim 1, wherein said single chip is encapsulated in a smart card and said second instruction storage region is configurable to receive instructions from a smart card terminal.

3. A single chip integrated circuit having processing means arranged to process instructions supplied from storage means, characterized in that

said storage means comprises a first storage region and a second storage region;

first instructions are selectively supplied to said processing means from said first storage region and said second region; and

enabling means are arranged to

enable said processing means to be responsive to privileged instructions if said first instructions are received from said first storage region, and

to disable said processing means from being responsive to said p rivileged instructions if said first instructions are received from said second storage region,

including paged addressing means arranged to supply addresses to an instruction storage region, wherein said paged addressing means is changeable only by protected instructions supplied from said first storage region.

4. A single chip integrated circuit having processing means arranged to process instructions supplied from storage means, characterized in that

said storage means comprises a first storage region and a second storage region;

first instructions are selectively supplied to said processing means from said first storage region and said second region; and

enabling means are arranged to

enable said processing means to be responsive to privileged instructions if said first instructions are received from said first storage region, and

to disable said processing means from being responsive to said privileged instructions if said first instructions are received from said second storage region, having a plurality of processing means wherein said first storage region includes multiplexing means arranged to select destination processing means for receiving instructions.

5. A circuit according to claim 4, wherein a first destination processing means is arranged to receive and decode instructions from said first storage region at a first instruction rate and a second destination processing means as arranged to receive and decode instructions from said first storage region at a second instruction rate.

6. A method of processing instructions read from storage means, characterized in that

said storage means comprises a single chip integrated circuit having first storage region and a second storage region;

first instructions are selectively supplied to a processing means from said storage regions; and

enabling means are arranged to

enable said processing means to be responsive to privileged instructions if said first instructions are received from said first storage region, and

said enabling means are arranged to disable said processing means from being responsive to said privileged instructions if said first instructions are received from said second storage region.

7. A method of processing instructions read from storage means, characterized in that

said storage means comprises first storage region and a second storage region;

first instructions are selectively supplied to a processing means from said storage regions; and

enabling means are arranged to

enable said processing means to be responsive to privileged instructions if said first instructions are received from said first storage region, and

said enabling means are arranged to disable said processing means from being responsive to said privileged instructions if said first instructions are received from said second storage region,

wherein regions of memory are divided into addressable pages and pace selection is controlled in response to instructions from said first storage region.

8. A method according to claim 7, wherein said processing means is configured to select a source of instructions and protected instructions are prevented from being executed.

9. A method of processing instructions read from storage means, characterized in that

said storage means comprises first storage region and a second storage region;

first instructions are selectively supplied to a processing means from said storage regions; and

enabling means are arranged to

enable said processing means to be responsive to privileged instructions if said first instructions are received from said first storage region, and

said enabling means are arranged to disable said processing means from being responsive to said privileged instructions if said first instructions are received from said second storage region,

wherein said processing means is configured to select a source of instructions and protected instructions are prevented from being executed,

wherein said protected instructions are selectively prevented from being executed in response to a control signal from decoding means.

10. A method according to claim 9 wherein a processing means is a cryptographic processing means.