Method of performing an extensive diagnostic test in conjunction with a bios test routine

• US 6,035,420 A
• Filed: 10/01/1997
• Issued: 03/07/2000
• Est. Priority Date: 10/01/1997
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micro Electronics Incorporated
• Inventors: Wu, Wei, Liu, Ji-hwan, Starr, Lowell
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Hamdan, Wasseem H.
• Application Number:
  US08/942,463
• Time in Patent Office: 888 Days
• Field of Search: 714/36, 714/46, 714/44, 714/42, 714/43, 714/25, 714/32, 714/34, 714/718, 714/719, 714/720, 714/739
• US Class Current: 714/25
• CPC Class Codes: G06F 11/2284 by power-on test, e.g. power-on self test [POST]
• CPC Class Codes: G11C 29/08 Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing

Abstract

A BIOS testing routine is initiated. Control is transferred to a diagnostic routine. The diagnostic routine performs a series of test in which a plurality of components are examined. In one embodiment, a random access/random data memory test is performed on a block of memory. Subsequently, control is transferred to the BIOS testing routine.

Claims

1. The method of testing a computer comprising:

initiating a BIOS testing routine;

transferring control to a diagnostic test routine in the normal course of BIOS testing;

performing said diagnostic test routine in which a plurality of components are examined, said diagostic test routine comprising

creating a temporary table of data from a smaller table of stored pseudo random data, wherein said temporary table is larger than said smaller table of stored pseudo random data,

determining a set of address blocks by logically dividing a memory under test into a set of continuous address arrays, wherein a total number of address blocks in said set of address blocks is equal to a total number of entries on said tempory table,

writing data from said temporary table into each address block of said set of address blocks in a pseudo random order according to data from said temporary table, and

comparing data stored in said memory under test to data written to said memory under test; and

resuming said BIOS testing routine.

2. The method of claim 1 wherein performing said diagnostic test routine comprises testing a central processing unit, a peripheral component, an interconnect system, memory and system power.

3. The method of claim 1 further comprising:

detecting a user interrupt during performance of said diagnostic test routine; and

initiating a manual diagnostic mode wherein user input is used to perform further diagnostic tests.

4. The method of claim 1 wherein said diagnostic test routine is performed if said BIOS testing routine is in itiated from a cold boot.

5. The method of claim 1 further comprising:

re-initiating said BIOS testing routine in response to a warm boot; and

bypassing performance of said diagnostic test routine.

6. A method of testing computer memory comprising:

creating a temporary table of data from a smaller table of stored pseudo random data, wherein said temporary table is larger than said smaller table of stored pseudo random data;

determining a set of address blocks by logically dividing memory under test into a set of continuous address arrays, wherein a total number of address blocks in said set of address blocks is equal to a total number of entries on said temporary table;

writing data from said temporary table into each address block of said set of address blocks in a pseudo random order according to data from said temporary table; and

comparing data stored in said memory under test to data written to said memory under test.

7. The method of claim 6 wherein each entry in said smaller table of stored pseudo random data comprises a first number of digits and wherein said smaller table of stored pseudo random data comprises one entry for each possible value of said first number of digits and where in said creating of s aid temporary table further comprises determining a set of temporary table entries having a second number of digits wherein said second number of digits is equal to twice said first number of digits.

8. The method of claim 7 wherein said step of determining said set of temporary value entries further comprises sequentially attaching each entry in said smaller table of stored pseudo random data as a set of most significant bits with each entry in said smaller table of stored pseudo random data as a set of least significant bits such that said temporary table comprises an entry for each possible value of said second number of digits.

9. The method of claim 8 wherein said writing data from said temporary table comprises:

determining a block address size equal to a total number of memory addresses under test divided by a number of entries in said temporary table;

reading a first entry from said temporary table;

determining a first block address by multiplying said first entry times said block address size; and

writing a series of data from said temporary table to a set of consecutive addresses beginning with said first block address.

10. The method of claim 9 further comprising:

reading a second entry from said temporary table;

determining second block address by multiplying said second entry times said block address size; and

writing a second series of data from said temporary table to a set of consecutive addresses beginning with said second block address.