Apparatus for deinterleaving and output-processing decoded data in a trellis decoder

• US 6,035,428 A
• Filed: 03/31/1998
• Issued: 03/07/2000
• Est. Priority Date: 03/31/1997
• Status: Expired due to Fees

• Current Assignee: Daewoo Electronics Company Limited (Dayou Holdings Co.,Ltd.)
• Original Assignee: Daewoo Electronics Company Limited (Dayou Holdings Co.,Ltd.)
• Inventors: Jekal, Heon
• Primary Examiner(s): Baker, Stephen M.
• Application Number:
  US09/052,550
• Time in Patent Office: 707 Days
• Field of Search: 714/702, 714/788, 714/792
• US Class Current: 714/702
• CPC Class Codes: H03M 13/253 with concatenated codes
• CPC Class Codes: H03M 13/256 with trellis coding, e.g. with convolutional codes and TCM
• CPC Class Codes: H03M 13/2732 Convolutional interleaver; Interleavers using shift-registers or delay lines like, e.g. Ramsey type interleaver
• CPC Class Codes: H03M 13/2936 comprising an outer Reed-Solomon code and an inner convolutional code
• CPC Class Codes: H03M 13/6538 ATSC VBS systems
• CPC Class Codes: H04L 27/02 Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation H04L27/32 takes precedence
• CPC Class Codes: H04L 27/3405 Modifications of the signal space to increase the efficiency of transmission, e.g. reduction of the bit error rate, bandwidth, or average power
• CPC Class Codes: H04L 27/38 Demodulator circuits; Receiver circuits

Abstract

An apparatus deinterleaves decoded symbols and outputs the deinterleaved symbols in an appropriate form for external devices. In order to achieve the deinterleaving and outputting processes, the apparatus sequentially stores the decoded symbols in response to enable signals and produces output data of P bits based on the stored decoded symbols by using two memory groups which alternately perform the storing and the producing processes. The operations of the two memory groups are controlled by an input control block and an output control block. The input control block produces the enable signals to control the two memory groups to thereby sequentially store the decoded symbols to the two memory groups. The output control block selects one of outputs provided from the two memory groups and provides the selected output as the output data of P bits.

Claims

1. An apparatus, for use in a trellis decoder, for deinterleaving decoded symbols produced by decoding convolutionally encoded symbols which have been M symbol interleaved, and providing output data of P bits based on the deinterleaved decoded symbols, wherein each symbol contains K bits, M, K and P being positive integers, respectively, which comprises:

two memory groups for sequentially storing the decoded symbols in response to enable signals and producing the output data of P bits based on the stored decoded symbols, wherein the two memory groups alternately perform the storing and the producing processes;

input control means for producing the enable signals to control the two memory groups to thereby sequentially store the decoded symbols to the two memory groups; and

output control means for selecting one of outputs provided from the two memory groups and providing the selected output as the output data of P bits.

2. The apparatus as recited in claim 1, wherein P is a multiple of K.

3. The apparatus as recited in claim 2, wherein each of the two memory groups contains M number of storage units, each of the storage units fully reserving the data of P bits and sequentially operating in response to the enable signals.

4. The apparatus as recited in claim 3, wherein each of the storage units employs a serial-input-parallel-output shift register which receives the decoded symbols on a unit of K bits and outputs the stored symbols therein on a unit of P bits.

5. The apparatus as recited in claim 4, wherein the decoded symbols stored at each of the storage units correspond to the convolutionally encoded symbols which have been encoded at a same encoder.

6. The apparatus as recited in claim 1 further comprising a flag signal generator for producing flag signals representing information for the output data provided via the output control means.

7. The apparatus as recited in claim 6, wherein the flag signal generator includes:

means for producing a SFLAG signal representing whether a segment synchronous signal is outputted or not; and

means for generating a FLAG signal depicting whether valid data is outputted or not.