Method for making a DRAM cell with grooved transfer device

• US 6,037,194 A
• Filed: 03/29/1999
• Issued: 03/14/2000
• Est. Priority Date: 04/07/1998
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Hakey, Mark C., Bronner, Gary B., Furukawa, Toshiharu, Horak, David V., Holmes, Steven J., Mandelman, Jack A., Rabidoux, Paul A.
• Primary Examiner(s): Chaudhari, Chandra
• Assistant Examiner(s): Thompson, Craig
• Application Number:
  US09/281,136
• Time in Patent Office: 351 Days
• Field of Search: 438/244, 438/243, 438/142, 438/175, 438/147
• US Class Current: 438/147
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/488 Word lines

Abstract

A memory cell having a grooved gate formed in a sub-lithographic groove, and methods of making thereof are disclosed. The groove extends the channel length to include the groove sidewalls and width of the groove. Sidewall sections of the channel located along the gate sidewalls have a larger length than the bottom channel section length located along the gate bottom width. Thus, the memory device is primarily controlled by the sidewall channel sections, instead of the bottom channel section. The groove may be a stepped groove formed by a two step etch to further increase the channel length and may be formed centered along the gate conductor width.

Claims

1. A method of fabricating a semiconductor device comprising the steps of:

forming in a substrate a groove having a sub-lithograplic width;

forming a grooved gate in said groove, said grooved gate having sidewall portions and a bottom portion, and defining a channel located in said substrate along said gate sidewall and bottom portions, wherein sidewall sections of said channel located along said gate sidewall portions have a larger length than a bottom length of a bottom section of said channel located along said gate bottom portion; and

forming first and second regions in said substrate on opposite sides of said grooved gate, respectively.

2. The method of claim 1 further comprising forming an isolation region in said substrate to isolate said semiconductor device, said isolation region having a depth which is greater than a depth of said groove.

3. The method of claim 1 further comprising forming a deep trench capacitor in said substrate, said deep trench capacitor having a storage electrode electrically connected to one of said first and second regions.

4. The method of claim 1 further comprising forming a doped well region located between said substrate and said groove.

5. The method of claim 1, wherein the groove forming step includes the steps of:

forming a mask over said substrate;

patterning said mask to expose sub-lithographic portions of said substrate;

forming spacers over sidewalls of said mask to reduce a width of said exposed sub-lithographic substrate portions; and

etching said reduced sub-lithographic substrate portions to form said groove.

6. The method of claim 5, wherein the mask forming step forms a hybrid resist mask.

7. The method of claim 5, wherein the spacers forming step forms polymer spacers.

8. The method of claim 5, prior to the mask forming step, further comprising forming an oxide layer over said substrate.

9. The method of claim 1, wherein the groove forming step includes the steps of:

forming a mask over said substrate;

patterning said mask to expose sub-lithographic portions of said substrate;

etching sections of said exposed sub-lithographic substrate portions to form said grooves using x-ray lithography.

10. The method of claim 1, prior to the grooved gate forming step, further comprising forming a gate oxide in said groove.

11. The method of claim 1, wherein the grooved gate forming step includes the steps of:

forming a mask over said substrate;

patterning said mask to expose portions of said substrate that include said groove;

forming a gate stack in said expose substrate portions.

12. The method of claim 11, wherein the gate stack forming step includes the steps of:

forming said grooved gate in said expose substrate portions;

forming a gate conductor over said grooved gate; and

forming a cover over top and sidewalls of said gate conductor and sidewalls of said grooved gate.

13. The method of claim 12, prior to the cover forming step, further comprising the steps of:

removing the mask; and

implanting impurities to form said first and second regions self-aligned to said grooved gate.

14. The method of claim 1, wherein the groove forming step includes the steps of:

forming an insulating layer over said substrate;

forming a mask over said insulating layer;

patterning said mask to expose sub-lithographic portions of said substrate;

removing said mask to expose said insulating layer;

forming spacers over sidewalls of said insulating layer to reduce a width of said exposed sub-lithographic substrate portions; and

etching said reduced sub-lithographic substrate portions to form said grooves.

15. The method of claim 1, wherein the groove forming step includes etching said substrate using phase-shift lithography.

16. The method of claim 1, wherein the groove forming step includes the steps of:

forming an oxide layer over said substrate;

forming a mask over said oxide layer;

patterning said mask to form an opening in said oxide layer for exposing portions of said substrate, said portions having a width equaling a feature size;

forming spacers over sidewalls of said oxide layer to reduce a width of said opening to a sub-lithographic size; and

etching said parts of said substrate exposed through said sub-lithographic opening to form said groove which is approximately centered in said opening.

17. The method of claim 16, wherein the groove forming step further includes, after the mask patterning step, removing said mask.

18. The method of claim 16, the grooved gate forming step comprises the steps of:

removing said spacers after forming said groove to expose said groove and lateral portions of said substrate; and

filling said opening with a gate stack including said gated groove formed in said groove and lower portions of said opening, a gate conductor formed over said grooved gate, and a cover formed over said gate conductor.

19. The method of claim 16, the filling step comprises the steps of:

filling said opening including said groove with intrinsic polysilicon;

recessing said intrinsic polysilicon into said opening;

doping said intrinsic polysilicon with impurities;

forming said gate conductor over said doped polysilicon in said opening;

recessing said gate conductor in said opening; and

forming, said cover over said gate conductor in said opening.

20. The method of claim 1, wherein the grooved gate forming step defines said channel to have a width which is substantially equal to said length of said groove.

21. The method of claim 1, wherein the grooved gate forming step defines said channel to have a length-which includes a width of said gate bottom portion.

22. The method of claim 1, wherein the grooved gate forming step defines said channel to have a length which includes a width of said gate bottom portion and a depth of said groove.

23. The method of claim 1, wherein the grooved gate forming step defines said channel so that one of said channel sidewall sections located along one of said gate sidewall portions has a larger length than said bottom length of said bottom channel section.

24. The method of claim 1, wherein the first and second regions forming step forms said first and second regions along a length of said groove.

25. The method of claim 1, wherein the first and second regions forming step separates said first and second regions from said groove by top lateral sections of said channel, and the grooved gate forming step extends said grooved gate over said top lateral channel sections to said first and second regions.

26. The method of claim 1, wherein the grooved gate forming step extends said grooved gate over top lateral channel sections that separate said grooved gate from said first and second regions.

27. The method of claim 26, wherein the grooved gate forming step extends a length of said channel to include distances of said top lateral channel sections, said channel sidewall sections and said channel bottom section.

28. The method of claim 1, wherein the groove forming step forms a stepped groove and the grooved gate forming step forms a stepped grooved gate so that each of said gate sidewalls are separated by a lateral step into top and bottom sidewall parts.

29. The method of claim 28, wherein the grooved gate forming step forms said stepped grooved gate so that a distance between said top sidewall parts is larger than a distance between said bottom sidewall parts.

30. The method of claim 28, wherein the groove forming step that forms said stepped groove includes the steps of:

forming a dielectric layer over said substrate;

selectively etching said dielectric layer to form an opening therein having a first width that exposes portions of said substrate;

forming a resist over sidewalls of said opening to reduce said first width of said opening to a second width;

etching the exposed portions of said substrate to form a groove therein having a width that equals said second width;

removing the resist from the sidewalls of said opening; and

etching said substrate to form said stepped groove having a lower width equaling said second width and an upper width equaling said first width.

31. The method of claim 28, wherein the groove forming step that forms said stepped groove includes the steps of:

forming a dielectric layer over said substrate;

selectively etching said dielectric layer to form a first opening, which exposes a first portion of said substrate;

forming a first pair of spacers on sidewalls of said first opening to form a second opening which is narrower than said first opening;

forming a second pair of spacers on said first pair of spacers to form a third opening which is narrower than said second opening;

etching said substrate through said third opening;

removing said second pair of spacers; and

etching said substrate through said second opening.

32. The method of claim 1, wherein the groove forming step forms said groove in a centered position between said first and second regions.

33. The method of claim 1, wherein the first and second regions forming step forms said first and second regions which are self aligned to said grooved gate.

34. The method of claim 1, wherein the first and second regions forming step is performed prior to the groove forming step.

35. A method of manufacturing a memory cell comprising the steps of:

forming a deep trench capacitor in a substrate doped with a first type of impurity, said deep trench capacitor having a plate electrode formed in said substrate and a storage electrode;

forming first and second regions doped with a second type of impurity in said substrate, said first region being connected to said storage node of said deep trench capacitor;

forming a groove in said substrate between said first and second regions; and

forming a grooved gate in said groove and beyond said groove extending a lateral distance over said substrate to control a resistance of a channel located in said substrate between said first and second regions;

said groove gate extending a length of said channel to include sidewalls of said groove, a width of said groove, and said lateral distance.