Method for growing an epitaxial layer of material using a high temperature initial growth phase and a low temperature bulk growth phase

• US 6,037,202 A
• Filed: 08/18/1997
• Issued: 03/14/2000
• Est. Priority Date: 09/28/1995
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Witek, Keith E.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): LEBENTRITT, MICHAEL
• Application Number:
  US08/914,035
• Time in Patent Office: 939 Days
• Field of Search: 438/489, 438/212, 438/213, 438/270
• US Class Current: 438/212
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78657 SOS transistors
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A method for forming a trench transistor structure begins by forming a buried layers (12 and 16) and a doped well (22) in a substrate (10) via epitaxial growth processing. A trench region (24) is then etched into the substrate (10) to expose a the layer (12). A conductive sidewall spacer (28) is formed within the trench (24) as a gate electrode. The spacer (28) gates a first transistor (12, 28, 32) located adjacent a first half of the trench (24) and a second transistor (12, 28, 34) located adjacent a second half of the trench (24). Region (12) is a common electrode wherein the channel regions of both the first and second transistor are coupled in a serial manner through the region (12).

Claims

1. A method for growing a layer of material, the method comprising the steps of:

providing a substrate having an exposed surface;

placing the substrate into a chamber at a low temperature;

removing oxygen from the chamber;

exposing the substrate simultaneously to a first growth gas and an etching gas wherein;

(1) a growth rate of the exposed surface due to the first growth gas is less than an etch rate of the exposed surface due to the etching gas when the chamber is set at the low temperature, whereby material is etched from the exposed surface when the chamber is at the low temperature; and

(2) a growth rate of the exposed surface due to the first growth gas is greater than an etch rate of the exposed surface due to the etching gas when at a high temperature greater than the low temperature so that material is grown on the exposed surface when the chamber is set to the high temperature;

ramping the temperature of the chamber from the low temperature to the high temperature over a first period of time while both the etchant gas and the first growth gas are present within the chamber whereby the etch rate is reduced relative to the growth rate during the ramp so that the etch rate becomes less than the growth rate;

removing the first growth gas from the chamber and replacing the first growth gas with a second growth gas capable of providing epitaxial growth at a temperature lower than the high temperature; and

reducing the temperature from the high temperature to the temperature lower than the high temperature to allow epitaxial growth to continue at the temperature lower than the high temperature to complete formation of the layer of material.

2. The method of claim 1 further comprising:

forming a doped region within the substrate and close to the exposed surface of the substrate; and

growing the layer of material on top of the doped region to form the doped region as a buried doped region located below the layer of material.

3. A method for growing a layer of material, the method comprising the steps of:

(a) placing a semiconductor wafer into a chamber at a first temperature;

(b) ramping a temperature of the chamber to a second temperature which is greater than the first temperature;

(c) flowing a first growth gas into the chamber at or above the second temperature, the first growth gas resulting in a growth species and an etch species being present in the chamber whereby wafer cleaning from the etch species and material growth due to the first growth species are occurring simultaneously on the wafer which is located in the chamber;

(d) reducing the temperature of the chamber and replacing, at least partially, the first growth gas with a second growth gas which allows for continued material growth on the wafer at a lower temperature than a temperature obtained in step (c); and

(e) reducing the temperature and removing the wafer from the chamber after material growth is complete.

4. The method of claim 3 wherein one or more of the steps (a) and (b) comprise:

removing oxygen from the chamber to reduce native oxide formation on the wafer.

5. The method of claim 3 wherein the step (c) comprises:

flowing SiH₂ Cl₂ as the first growth gas.

6. The method of claim 3 wherein the step (c) comprises:

providing HCl as the etch species.

7. The method of claim 3 wherein the step (d) comprises:

providing Si₂ H₆ as the second growth gas.

8. The method of claim 3 wherein the step (d) comprises:

providing SiH₄ as the second growth gas.

9. The method of claim 3 wherein the step (c) comprises:

obtaining a chamber temperature of at least 800°

C. for a period of time.

10. The method of claim 3 wherein the step (d) comprises:

maintaining a chamber temperature of less 800°

C. for all time during step (d).

11. The method of claim 3 wherein the step (d) comprises:

maintaining a chamber temperature of less 600°

C. for all time during step (d).

12. The method of claim 3 further comprising:

forming a doped region within a substrate and close to the exposed surface of the substrate; and

using steps (a) through (e) to form the doped region as a buried doped region.

13. The method of claim 3 further comprising:

forming a first doped region within a substrate and close to the exposed surface of the substrate;

using steps (a) through (e) to form epitaxial material over the first doped region to make the first doped region a first buried doped region;

forming a second doped region over the first doped region;

using steps (a) through (e) to form epitaxial material over the second doped region to make the second doped region a second buried doped region overlying the first buried doped region.

14. The method of claim 13 further comprising:

forming a second buried doped region with an opposite conductivity type of the second buried doped region.

15. The method of claim 13 further comprising:

using the steps (a) through (e) to form a portion of an SRAM cell.

16. The method of claim 13 wherein the step (c) further comprises:

raising the temperature over time within step (c) wherein;

(1) initial stages of step (c) etch wafer material at an etch rate which is greater than a growth rate of new material; and

(2) later states of step (c) etch wafer material at an etch rate which is less than a growth rate of new material.

17. A method for growing a layer of material, the method comprising the steps of:

providing a substrate;

doping a portion of the substrate to form a doped region near a surface of the substrate;

growing a first portion of the layer of material on the substrate at a temperature greater than 800°

C. using a growth gas, the growth gas generating both an etch species which cleans the substrate and a growth species which grows a portion of the layer of material onto the substrate;

changing the growth gas to another growth gas wherein the another growth gas allows for a remainder of the layer of material to be grown at a temperature which is less than 600°

C.; and

wherein formation of the layer of material makes the doped region a buried region.

18. The method of claim 17 wherein the step of forming the doped region comprises:

forming the doped region as a composite doped region wherein a top portion of the doped region is a first conductivity type and a second portion of the doped region is a second conductivity type different from the first conductivity type.

19. The method of claim 17 wherein the buried region is a source/drain electrode in an SRAM cell.

20. The method of claim 17 wherein the step of changing the growth gas comprises growing a portion of the remainder of the layer of material at a temperature of roughly equal to 400°

C.

21. A method for growing a layer of material, the method comprising the steps of:

(a) placing a semiconductor wafer into a chamber at a first temperature;

(b) ramping a temperature of the chamber to a second temperature which is greater than the first temperature;

(c) flowing a first growth gas into the chamber at or above the second temperature, the first growth gas resulting in a growth species and an etch species being present in the chamber whereby wafer cleaning from the etch species and material growth due to the first growth species are occurring simultaneously on the wafer which is located in the chamber;

(d) reducing the temperature of the chamber and replacing, at least partially, the first growth gas with a second growth gas which allows for continued material growth on the wafer at a lower temperature than a temperature obtained in step (c), wherein this step (d) maintains a chamber temperature of less 600°

C. for a substantial period of time while the second growth gas is provided into the chamber; and

(e) reducing the temperature and removing the wafer from the chamber after material growth is complete wherein the material growth is used to form a plurality of separate buried layers within the semiconductor wafer.