Silicon and arsenic double implanted pre-amorphization process for salicide technology

• US 6,037,204 A
• Filed: 08/07/1998
• Issued: 03/14/2000
• Est. Priority Date: 08/07/1998
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Shou-Zen, Ho, Chin-Hsiung, Tsai, Chaochieh, Lin, Cheng Kun
• Primary Examiner(s): BOOTH, RICHARD A
• Application Number:
  US09/131,321
• Time in Patent Office: 585 Days
• Field of Search: 438/585, 438/301, 438/303, 438/305, 438/528, 438/231, 438/592
• US Class Current: 438/231
• CPC Class Codes: H01L 21/2236 from or into a plasma phase
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/28052 the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer formed by metal ion implantation H01L21/28044
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/823835 silicided or salicided gate conductors
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518

Abstract

A method for forming salicide contacts and polycide conductive lines in integrated circuits is described which employs the ion implantation of both silicon and arsenic into polysilicon structures and into source/drain MOSFET elements is described. The method is effective in reducing gate-to-source/drain bridging in the manufacture of sub-micron CMOS integrated circuits and improving the conductivity of sub-micron wide polycide lines. Silicon is implanted into the polysilicon and into the source/drain surfaces forming a amorphized surface layer. Next a low dose, low energy arsenic implant is administered into the amorphized layer. The low dose shallow arsenic implant in concert with the amorphized layer initiates an equalized formation of titanium silicide over both NMOS and PMOS devices in CMOS integrated circuits without degradation of the PMOS devices. Amorphization by the electrically neutral silicon ions permits the use of a lower dose of arsenic than would be required if arsenic alone were implanted. In addition to amorphization, the implanted silicon prevents the formation of microvoids by providing silicon towards titanium silicide formation. The combined amorphization effect of the silicon and arsenic implants also facilitates a silicide phase transition on sub-micron wide polycide lines thereby improving their conductivity.

Claims

1. A method for forming contacts to p- and n-channel self-aligned polysilicon gate MOSFETs comprising:

(a) providing a silicon wafer having at least one p-channel self aligned polysilicon gate MOSFET and at least one n-channel self-aligned polysilicon gate MOSFET formed within and upon its surface, said at least one p-channel self aligned polysilicon gate MOSFET and said at least one n-channel self-aligned polysilicon gate MOSFET having impurity doped source/drain active areas and polysilicon gate electrodes with adjacent insulative sidewall spacers;

(b) Implanting silicon atoms into said silicon wafer thereby forming amorphous regions on said source/drain areas and said gate electrodes;

(c) implanting arsenic atoms into said amorphous regions thereby forming arsenic doped regions and wherein said arsenic doped regions lie within said amorphous regions;

(d) depositing a metal layer on said silicon wafer;

(e) depositing a protective layer over said metal layer;

(f) performing a first thermal anneal of said silicon wafer whereby a portion of said metal layer reacts with said polysilicon layer to form a silicide;

(g) etching said wafer with an aqueous etchant thereby removing said protective layer and residual said metal layer;

(h) performing a second thermal anneal of said silicon wafer;

(i) depositing an insulative layer over said silicon wafer;

(j) etching contact openings in said insulative layer; and

(k) depositing a conductive material into said openings thereby forming contacts.

2. The method of claim 1 wherein said silicon atoms are implanted at a dose of between about 1×

10¹⁴ and 2×

10¹⁵ atoms per cm² and at an energy of between about 20 and 50 keV.

3. The method of claim 1 wherein said arsenic atoms are implanted at a dose of between about 5×

10¹³ and 5×

10¹⁴ atoms per cm² and at an energy of between about 5 and 10 keV.

4. The method of claim 1 wherein said metal layer is selected from the group consisting of titanium, cobalt, molybdenum, and tungsten.

5. The method of claim 1 wherein said protective layer is titanium nitride.

6. The method of claim 1 wherein said metal layer is deposited at a thickness of between about 275 and 400 Angstroms and said protective layer is deposited at a thickness of 200 Angstroms or thereabout.

7. The method of claim 1 wherein said first thermal anneal is performed by rapid thermal annealing at a temperature between about 675 and 740°

C. for a period of between about 10 and 40 seconds in an ambient of nitrogen.

8. The method of claim 1 wherein said second thermal anneal is performed by rapid thermal annealing at a temperature between about 830°

C. and 950°

C. for a period of between about 10 and 40 seconds.

9. A method for forming a polycide gate electrode comprising:

(a) providing a silicon wafer having an active area;

(b) forming a gate oxide;

(c) forming a polysilicon gate electrode on said gate oxide;

(b) Implanting silicon atoms into said silicon wafer thereby forming an amorphous region on said polysilicon gate electrode;

(c) implanting arsenic atoms into said amorphous region thereby forming an arsenic doped region, wherein said arsenic doped region is confined within said amorphous region;

(d) depositing a metal layer on said silicon wafer;

(e) depositing a protective layer over said metal layer;

(f) performing a first thermal anneal of said silicon wafer whereby a portion of said metal layer reacts with said polysilicon gate electrode forming a silicide;

(g) etching said wafer with an aqueous etchant, thereby removing said protective layer and residual said metal layer and forming a polycide gate electrode; and

(h) performing a second thermal anneal of said silicon wafer.

10. The method of claim 9 wherein said silicon atoms are implanted at a dose of between about 1×

10¹⁴ and 2×

10¹⁵ atoms per cm² and at an energy of between about 20 and 50 keV.

11. The method of claim 9 wherein said arsenic atoms are implanted at a dose of between about 5×

10¹³ and 5×

10¹⁴ atoms per cm² and at an energy of between about 5 and 10 keV.

12. The method of claim 9 wherein said metal layer is selected from the group consisting of titanium, cobalt, molybdenum, and tungsten.

13. The method of claim 9 wherein said protective layer is titanium nitride.

14. The method of claim 9 wherein said metal layer is deposited at a thickness of between about 275 and 400 Angstroms and said protective layer is deposited at a thickness of 200 Angstroms or thereabout.

15. The method of claim 9 wherein said first thermal anneal is performed by rapid thermal annealing at a temperature between about 675 and 740°

C. for a period of between about 10 and 40 seconds in an ambient of nitrogen.

16. The method of claim 9 wherein said second thermal anneal is performed by rapid thermal annealing at a temperature between about 830 and 950°

C. for a period of between about 10 and 40 seconds.

17. The method of claim 9 wherein the width of said polycide electrode is less than 1 micron.

18. A method for forming conductive polycide lines comprising:

(a) providing a silicon wafer having an insulative layer;

(b) forming a polysilicon line on said insulative layer;

(c) Implanting silicon atoms into said polysilicon line thereby forming an amorphous region;

(d) implanting arsenic atoms into said amorphous region thereby forming an arsenic doped region, wherein said arsenic doped region is confined within said amorphous region;

(e) depositing a metal layer on said silicon wafer;

(f) depositing a protective layer over said metal layer;

(g) performing a first thermal anneal of said silicon wafer whereby a portion of said metal layer reacts with said polysilicon line forming a silicide;

(h) etching said wafer with an aqueous etchant, thereby removing said protective layer, said residual metal layer and forming a polycide line; and

(i) performing a second thermal anneal of said silicon wafer.

19. The method of claim 18 wherein said silicon atoms are implanted at a dose of between about 1×

10¹⁴ and 2×

10¹⁵ atoms per cm² and at an energy of between about 20 and 50 keV.

20. The method of claim 18 wherein said arsenic atoms are implanted at a dose of between about 5×

10¹³ and 5×

10¹⁴ atoms per cm² and at an energy of between about 5 and 10 keV.

21. The method of claim 18 wherein said metal layer is selected from the group consisting of titanium, cobalt, molybdenum, and tungsten.

22. The method of claim 18 wherein said protective layer is titanium nitride.

23. The method of claim 18 wherein said metal layer is deposited at a thickness of between about 275 and 400 Angstroms and said protective layer is deposited at a thickness of 200 Angstroms or thereabout.

24. The method of claim 18 wherein said first thermal anneal is performed by rapid thermal annealing at a temperature between about 675 and 740°

C. for a period of between about 10 and 40 seconds in an ambient of nitrogen.

25. The method of claim 18 wherein said second thermal anneal is performed by rapid thermal annealing at a temperature between about 830 and 950°

C. for a period of between about 10 and 40 seconds.

26. The method of claim 18 wherein the width of said polycide line is less than 1 micron.