Memory cell with transfer device node in selective polysilicon

• US 6,037,210 A
• Filed: 03/30/1998
• Issued: 03/14/2000
• Est. Priority Date: 10/16/1997
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Leas, James M.
• Primary Examiner(s): Monin, Jr., Donald L.
• Assistant Examiner(s): PHAM, HOAI V
• Application Number:
  US09/049,947
• Time in Patent Office: 715 Days
• Field of Search: 438/245, 438/246, 438/248, 438/249, 438/243, 438/386, 257/301, 257/305
• US Class Current: 438/245
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate
• CPC Class Codes: H10B 12/373 the capacitor extending under or around the transistor

Abstract

A memory cell is constructed with one electrode of the transfer device extending over a trench capacitor, saving about 6.5% of cell area. Selective polysilicon for a strap seeded from the trench is grown in the same step in which selective single crystal silicon seeded from the substrate is grown for the transfer device. At least a portion of the node diffusion is located in single crystal epitaxial silicon extending over the trench. The process eliminates the need for a separate strap masking step.

Claims

1. A method of fabricating a semiconductor structure, comprising:

providing a semiconductor substrate;

forming a trench comprising a doped polycrystalline semiconductor electrode in said semiconductor substrate, said trench having two edges;

growing a layer of epitaxial semiconductor above said substrate and above said trench, wherein said layer of epitaxial semiconductor comprises a single crystalline portion and a polycrystalline portion, wherein said polycrystalline portion extends exclusively over said polycrystalline semiconductor electrode in said trench between vertical axes extending from said two edges, and wherein said single crystalline portion extends over a portion of said polycrystalline portion between said vertical axes extending from said two edges;

forming a node diffusion in said layer of epitaxial semiconductor having a first portion formed in an upper region of said polycrystalline portion of said layer and a second portion formed in an upper region of said single crystalline portion of said layer of epitaxial semiconductor which includes said portion which extends over said doped polycrystalline portion; and

a gate having a gate edge aligned over one of said two trench edges.

2. A method of fabricating a semiconductor structure comprising:

a) providing a semiconductor substrate;

b) forming a trench comprising a polycrystalline semiconductor electrode, said trench having two edges;

c) growing a layer of epitaxial semiconductor above said substrate and above said trench, wherein said layer of epitaxial semiconductor comprises a single crystalline portion and a polycrystalline portion, wherein said polycrystalline portion extends exclusively over said polycrystalline semiconductor electrode in said trench between vertical axes extending from said two edges, and wherein said single crystalline portion extends over a portion of said polycrystalline portion between said vertical axes extending from said two edges; and

d) forming a node diffusion in said layer of epitaxial semiconductor having a first portion formed in an upper region of said polycrystalline portion of said layer of epitaxial semiconductor and a second portion formed in an upper region of said single crystalline portion of said epitaxial layer which includes said portion which extends over said doped polycrystalline portion.