Method of fabricating self-aligned contact window which includes forming a undoped polysilicon spacer that extends into a recess of the gate structure

• US 6,037,228 A
• Filed: 02/12/1999
• Issued: 03/14/2000
• Est. Priority Date: 02/12/1999
• Status: Expired due to Fees

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Hsu, Shih-Ying
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): POMPEY, RON EVERETT
• Application Number:
  US09/249,501
• Time in Patent Office: 396 Days
• Field of Search: 438/230, 438/593, 438/595, 438/592, 438/303, 438/279, 438/634, 438/261, 257/382, 257/383, 257/900, 257/412
• US Class Current: 438/279
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

A method of fabricating a self-aligned contact window is described. A gate oxide layer, a conductive layer, a first oxide layer and an undoped polysilicon layer are successively formed on a substrate. These layers above are patterned to form a gate structure. A water clean step is performed, producing a recess in the first oxide layer. A second oxide layer is thermally formed on the surface of the gate structure. An undoped polysilicon spacer is formed on the sidewall of the gate structure and a portion of the undoped polysilicon spacer extends into the recess of the first oxide layer. A dielectric layer is formed over the substrate and using the undoped polysilicon spacer as an etching stop, a self-aligned contact window is formed to expose the source/drain region.

Claims

1. A method of fabricating a self-aligned contact window, comprising:

providing a substrate having a gate oxide layer;

forming a conductive layer, a first oxide layer and a first undoped polysilicon layer on the substrate;

patterning the first undoped polysilicon layer, the first oxide layer and the conductive layer to form a gate structure having a surface;

removing a portion of the first oxide layer to form a recess therein;

forming a second oxide layer on the surface of the gate structure;

forming an undoped polysilicon spacer on the sidewall of the gate structure such that the undoped polysilicon spacer extends into the recess of the first oxide layer;

forming a dielectric layer over the substrate; and

forming a self-aligned contact window within the dielectric layer to expose the substrate.

2. The method according to claim 1, wherein the first oxide layer includes TEOS oxide.

3. The method according to claim 2, wherein the TEOS oxide is formed by chemical vapor deposition.

4. The method according to claim 1, wherein a portion of the first oxide layer is removed by wet cleaning.

5. The method according to claim 4, wherein the wet cleaning is performed in a HF solution.

6. The method according to claim 1, wherein the second oxide layer is formed by thermal oxidation.

7. The method according to claim 1, wherein forming the undoped polysilicon spacer further comprises:

forming a second undoped polysilicon layer over the substrate; and

etching back the second undoped polysilicon layer to form an undoped polysilicon spacer on the sidewall of the gate structure.

8. The method according to claim 1, wherein forming the self-aligned contact window further comprises using the first undoped polysilicon layer as an etching stop to pattern the dielectric layer.

9. The method according to claim 1, wherein after forming the undoped polysilicon layer further comprises forming an anti-reflectivity coating layer.

10. The method according to claim 9, wherein the anti-reflectivity coating layer includes silicon-oxy-nitride (SiO_x N_y).

11. The method according to claim 1, wherein after forming the second oxide layer further comprises forming a lightly doped source/drain region in the substrate beside the gate structure.

12. The method according to claim 1, wherein after forming the polysilicon spacer further comprises forming a heavily doped source/drain region in the substrate beside the undoped polysilicon spacer.

13. The method according to claim 1, wherein the thickness of the first oxide layer is in a range of about 300-700 angstroms.

14. The method according to claim 1, wherein the thickness of the first undoped polysilicon layer is in a range of about 300-600 angstroms.

15. The method according to claim 1, wherein the thickness of the second oxide layer is in a range of about 100-150 angstroms.