Method of forming a smooth copper seed layer for a copper damascene structure

• US 6,037,258 A
• Filed: 05/07/1999
• Issued: 03/14/2000
• Est. Priority Date: 05/07/1999
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Chung-Shi, Yu, Chen-Hua
• Primary Examiner(s): Chaudhari, Chandra
• Assistant Examiner(s): KILDAY, LISA A
• Application Number:
  US09/307,206
• Time in Patent Office: 312 Days
• Field of Search: 438/758, 438/760, 438/765, 438/776, 438/774, 438/687
• US Class Current: 438/687
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 2221/1089 Stacks of seed layers

Abstract

A method for fabricating a copper interconnect structure, in a damascene type opening, comprised a thick copper layer, obtained via an electro-chemical deposition procedure, and comprised of an underlying, copper seed layer, featuring a smooth top surface topography, has been developed. The smooth top surface topography, of the underlying copper seed layer, is needed to allow the voidless deposition of the overlying, thick copper layer, and is also needed to allow the deposition of the overlying thick copper layer to be realized, with a surface that can survive a chemical mechanical polishing procedure, without the risk of unwanted dishing or spooning phenomena. The desirable, copper seed layer, is obtained via a process sequence that features: a plasma vapor deposition of a first copper seed layer; an argon purge procedure; and a second plasma vapor deposition of a second copper seed layer. The use of an argon purge, allows the increase in temperature, introduced by plasma bombardment, to be decreased, allowing a copper seed layer, featuring a smooth top surface topography, to be obtained.

Claims

1. A method of forming a metal structure, on a semiconductor substrate, comprising the steps of:

providing an insulator layer, on said semiconductor substrate, and providing an opening in said insulator layer, exposing an underlying conductive region;

depositing a barrier layer;

depositing a first copper seed layer, in a chamber of a cluster tool;

performing a cooling procedure to said semiconductor substrate, in situ, in said chamber of said cluster tool;

depositing a second copper seed layer, on said first copper seed layer, in situ, in said chamber of said cluster tool, to a thickness between about 500 to 1200 Angstroms, using a plasma vapor deposition procedure;

depositing a thick copper layer on said second copper layer, to a thickness between about 5000 to 16000 Angstroms, via a electro-chemical deposition procedure; and

removing regions of said thick copper layer, regions of said second copper seed layer, regions of said first copper seed layer, and regions of said barrier layer, from the top surface of said insulator layer, to form said metal structure, in the opening in said insulator layer.

2. The method of claim 1, wherein said underlying conductive region, exposed at the bottom of said contact hole, is an underlying metal interconnect structure, formed from either an aluminum based metal layer, a refractory metal layer, such as tungsten, or a metal silicide layer, such as a tungsten silicide layer.

3. The method of claim 1, wherein said opening, in said insulator layer can be a dual damascene opening, comprised of an upper, wide diameter opening, and a lower, narrow diameter opening.

4. The method of claim 1, wherein said barrier layer is either a tantalum layer, of a tantalum nitride layer, deposited in a first chamber of a cluster tool, using a plasma vapor deposition, (PVD), procedure, such as R.F. sputtering, to a thickness between about 100 to 600 Angstroms.

5. The method of claim 1, wherein said first copper seed layer is deposited in a second chamber of a cluster tool, using a PVD procedure, such as R.F. sputtering, to a thickness between about 500 to 1200 Angstroms.

6. The method of claim 1, wherein said cooling procedure is performed in situ, in a second chamber of a cluster tool, via use of an argon purge, applied to the front side, as well as to the backside, of said semiconductor substrate.

7. The method of claim 1, wherein said metal structure is formed in the opening in said insulator layer, via removal of regions of said thick copper layer, regions of said second portion, copper seed layer, regions of said first copper seed layer, and regions of said barrier layer, from the top surface of said insulator layer, using a chemical mechanical polishing procedure.

8. A method of forming a dual damascene, copper structure, in a dual damascene opening in an insulator layer, comprised of an underlying copper seed layer, featuring a smooth top surface topography, resulting from a three step plasma vapor deposition sequence, and comprised of an overlying electro-chemical deposited copper layer, comprising the steps of:

forming said dual damascene opening, in said insulator layer, exposing a portion of a top surface of a conductive region, on a semiconductor substrate;

depositing a barrier layer, in a first chamber of a cluster tool;

on the top surface of said insulator layer;

coating the sides of the dual damascene opening; and

overlying and contacting the portion of the top surface of said conductive region, exposed at the bottom of said dual damascene opening;

depositing a first copper seed layer, on said barrier layer, in a second chamber of the cluster tool;

performing an argon purge procedure, in situ in said second chamber of the cluster tool, to cool said semiconductor substrate;

depositing a second copper seed layer, in situ, in said second chamber of the cluster tool, to a thickness between about 500 to 1200 Angstroms, using a plasma vapor deposition procedure, with said second copper seed layer having a smooth top surface topography;

depositing a thick copper layer, via an electro-chemical deposition, (ECD), procedure, on said second copper seed layer, completely filling said dual damascene opening; and

performing a chemical mechanical polishing procedure, to remove regions of said thick copper layer, regions of said second copper seed layer, regions of said first copper seed layer, and regions of said barrier layer, from the top surface of said insulator layer, creating said dual damascene copper structure, in said dual damascene opening.

9. The method of claim 8, wherein said conductive region, at the bottom of said dual damascene opening, is an underlying metal interconnect structure, formed from either an aluminum based layer, a tungsten layer, of a tungsten silicide layer.

10. The method of claim 8, wherein said barrier layer is a tantalum layer, obtained via a plasma vapor deposition, (PVD), procedure, such as R.F. sputtering, to a thickness between about 100 to 600 Angstroms.

11. The method of claim 8, wherein said barrier layer is a tantalum nitride layer, obtained via PVD procedure, such as R.F. sputtering, to a thickness between about 100 to 600 Angstroms.

12. The method of claim 8, wherein said first copper seed layer is deposited using a PVD procedure, such as R.F. sputtering, to a thickness between about 500 to 1200 Angstroms.

13. The method of claim 8, wherein said argon purge procedure, is performed to both front side, and backside, of said semiconductor substrate.

14. The method of claim 8, wherein said thick copper laser is deposited using ECD procedures, to a thickness between about 5000 to 16000 Angstroms.