Semiconductor structures with trench contacts

• US 6,037,628 A
• Filed: 06/30/1997
• Issued: 03/14/2000
• Est. Priority Date: 06/30/1997
• Status: Expired due to Term

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Original Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Inventors: Huang, Qin
• Primary Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US08/885,922
• Time in Patent Office: 988 Days
• Field of Search: 257/377, 257/329, 257/330, 257/331, 257/332, 257/328
• US Class Current: 257/329
• CPC Class Codes: H01L 29/41716 Cathode or anode electrodes for thyristors
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/6634 with a recess formed by etching in the source/emitter contact region H01L29/66348 takes precedence; etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Semiconductor structures such as the trench and planar MOSFETs (UMOS), trench and planar IGBTs and trench MCTs using trenches to establish a conductor. Improved control of the parasitic transistor in the trench MOSFET is also achieved and cell size and pitch is reduced relative to conventional structures.

Claims

1. A semiconductor device comprising:

a wafer having at least one horizontal PN junction;

a pair of spaced trenches of a first electrically conducting material surrounded by insulation; and

a third trench filled completely with only a second conducting material intermediate said spaced trenches and extending deeper into said wafer than said spaced trenches, said third trench extending downwardly through said at least one horizontal PN junction without reaching a second PN junction vertically displaced from said at least one horizontal PN junction.

2. The device of claim 1 wherein each of said spaced trenches comprise polysilicon surrounded by an oxide.

3. The device of claim 1 wherein said third trench is filled with a metal.

4. The device of claim 1 further comprising borophosphosilicate glass insulating the conducting material in each of said trenches from each other.

5. A FET semiconductor structure comprising:

a polysilicon filled trench lined with a gate oxide bounding a source region, said source region overlying and in contact with a channel region, said channel region overlying and bordering a region of high concentration so that there is a material area of contact between said channel region and said region of high concentration; and

a metal contact with both the source and channel regions, wherein the metal extends downwardly a distance greater than the depth of the trench into contact with the channel region rather than laterally along the wafer surface into contact with the channel region so that the only substantial contact of the metal with the channel region is on a vertical surface.

6. A FET semiconductor device formed in a silicon wafer comprising:

a region of high concentration;

a channel region overlying and bordering said region of high concentration;

a source region overlying and in contact with said channel region;

a gate oxide lined first trench filled with polysilicon bounding said source region and said channel region;

a metal filled second trench is in direct contact with said source region, said channel region, and said region of high concentration and extending deeper into said wafer than said first trench.

7. The device of claim 6 further comprising borophosphosilicate glass insulating said polysilicon from said metal.

8. A FET semiconductor device formed in a silicon wafer comprising:

a region of high concentration;

a channel region overlying and bordering said region of high concentration;

a source region overlying and in contact with said channel region;

a gate oxide lined first trench filled with polysilicon bounding said source region and said channel region;

a metal filled second trench bounding said source region, said channel region, and said region of high concentration and extending deeper into said wafer than said first trench, said metal extending out from said second trench and overlying said first trench.

9. The device of claim 8 further comprising borophosphosilicate glass disposed over said first trench and between said metal and said first trench.