Semiconductor device

• US 6,037,632 A
• Filed: 11/05/1996
• Issued: 03/14/2000
• Est. Priority Date: 11/06/1995
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Omura, Ichiro, Ohashi, Hiromichi, Inoue, Tomoki
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Nadav, Ori
• Application Number:
  US08/744,212
• Time in Patent Office: 1,225 Days
• Field of Search: 257/139, 257/147, 257/341, 257/401, 257/490, 257/491, 257/492, 257/495, 257/496
• US Class Current: 257/341
• CPC Class Codes: H01L 21/74 Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/405 Resistive arrangements, e.g. resistive or semi-insulating field plates
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/739 controlled by field-effect, e.g. bipolar static induction transistors [BSIT] unijunction transistors H01L29/705
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device is disclosed, which comprises a first main electrode, a second main electrode, a high-resistance semiconductor layer of first conductivity type interposed between the first main electrode and the second main electrode, and at least a buried layer of second conductivity type selectively formed in the semiconductor layer, extending at substantially right angles to a line connecting the first and second main electrodes, comprising a plurality strips functioning as current paths and set at a potential different from a potential of any other electrode when a depletion layer extending from a region near the first main electrode reaches the buried layer.

Claims

1. A semiconductor device comprising:

a first main electrode;

a second main electrode;

a high-resistance semiconductor layer of a first conductivity type interposed between said first main electrode and said second main electrode; and

a buried layer of a second conductivity type selectively formed in said high-resistance semiconductor layer of the first conductivity type, having a floated potential, and extending at substantially right angles to a line connecting said first and second main electrodes, and comprising a plurality of strips functioning as current paths and set at said floated potential different from a potential of any other electrode when a depletion layer extending from a region near said first main electrode reaches said buried layer of the second conductivity type,

wherein the following relations hold;

space="preserve" listing-type="equation">Vs=(BV-V.sub.1 -V.sub.2)/(M-1)V;

space="preserve" listing-type="equation">V.sub.1 ≧

Vs;

space="preserve" listing-type="equation">V.sub.2 ≧

Vs;

space="preserve" listing-type="equation">N.sub.1 <

1.897×

10.sup.18 ×

V.sub.1.sup.-1.35 cm.sup.-3 ;

space="preserve" listing-type="equation">N.sub.2 <

1.897×

10.sup.18 ×

V.sub.2.sup.-1.35 cm.sup.-3 ;

space="preserve" listing-type="equation">Ns<

1.897×

10.sup.18 ×

Vs.sup.-1.35 cm.sup.-3 ;

space="preserve" listing-type="equation">W.sub.1 <

1.1247×

10.sup.10 ×

N.sub.1.sup.-0.85 cm;

space="preserve" listing-type="equation">Ws<

1.1247×

10.sup.10 ×

Ns.sup.-0.85 cm; and

where

BV is the breakdown voltage between said first and second main electrodes;

M is the number of said buried layer of the second conductivity type between said first and second main electrodes;

V₁ is the voltage allotted to a first region of said high-resistance semiconductor layer of the first conductivity type between said first main electrode and said buried layer of the second conductivity type, said first region being located near said first main electrode;

N₁ is the impurities concentration of said first region of said high-resistance semiconductor layer of the first conductivity type;

W₁ is the thickness of said first region of said high-resistance semiconductor layer of the first conductivity type;

V₂ is the voltage allotted to a second region of said high-resistance semiconductor layer of the first conductivity type between said second main electrode and said buried layer of the second conductivity type, said second region being located near said second main electrode;

N₂ is the impurities concentration of said second region of said high-resistance semiconductor layer of the first conductivity type;

Vs is the voltage allotted to a third region of said high-resistance semiconductor layer of the first conductivity type, said third region is between said first and second regions of said high-resistance semiconductor layer of the first conductivity type;

Ns is the impurities concentration of said third region of said high-resistance semiconductor layer of the first conductivity type; and

Ws is the thickness of said third region of said high resistance semiconductor layer of the first conductivity type.

2. A semiconductor device comprising:

a first main electrode;

a second main electrode;

a high-resistance semiconductor layer of a first conductivity type interposed between said first main electrode and said second main electrode;

a current control structure formed in contact with said high-resistance semiconductor layer of the first conductivity type and having a control electrode for controlling the current flowing from said first main electrode to said second main electrode; and

a buried layer of a second conductivity type selectively formed in said high-resistance semiconductor layer of the first conductivity type, having a floated potential, and extending at substantially right angles to a line connecting said first and second main electrodes and comprising a plurality of strips functioning as current paths, and said plurality of strips are set at a floating potential different from a potential of any other electrode when a depletion layer extending from a region near said first main electrode reaches said buried layer of the second conductivity type,

wherein the following relations hold;

space="preserve" listing-type="equation">Vs=(BV-V.sub.1 -V.sub.2)/(M-1)V;

space="preserve" listing-type="equation">V.sub.1 ≧

Vs;

space="preserve" listing-type="equation">V.sub.2 ≧

Vs;

space="preserve" listing-type="equation">N.sub.1 <

1.897×

10.sup.18 ×

V.sub.1.sup.-1.35 cm.sup.-3 ;

space="preserve" listing-type="equation">N.sub.2 <

1.897×

10.sup.18 ×

V.sub.2.sup.-1.35 cm.sup.-3 ;

space="preserve" listing-type="equation">Ns<

1.897×

10.sup.18 ×

Vs.sup.-1.35 cm.sup.-3 ;

space="preserve" listing-type="equation">W.sub.1 <

1.1247×

10.sup.10 ×

N.sub.1.sup.-0.85 cm;

space="preserve" listing-type="equation">Ws<

1.1247×

10.sup.10 ×

Ns.sup.-0.85 cm; and

where

BV is the breakdown voltage between said first and second main electrodes;

M is the number of said buried layer of the second conductivity type between said first and second main electrodes;

V₁ is the voltage allotted to a first region of said high-resistance semiconductor layer of the first conductivity type between said first main electrode and said buried layer of the second conductivity type, said first region being located near said first main electrode;

N₁ is the impurities concentration of said first region of said high-resistance semiconductor layer of the first conductivity type;

W₁ is the thickness of said first region of said high-resistance semiconductor layer of the first conductivity type;

V₂ is the voltage allotted to a second region of said high-resistance semiconductor layer of the first conductivity type between said second main electrode and said buried layer of the second conductivity type, said second region being located near said second main electrode;

N₂ is the impurities concentration of said second region of said high-resistance semiconductor layer of the first conductivity type;

Vs is the voltage allotted to a third region of said high-resistance semiconductor layer of the first conductivity type, said third region is between said first and second regions of said high-resistance semiconductor layer of the first conductivity type;

Ns is the impurities concentration of said third region of said high-resistance semiconductor layer of the first conductivity type; and

Ws is the thickness of said third region of said high resistance semiconductor layer of the first conductivity type.

3. A semiconductor device comprising:

a drain layer;

a drain electrode formed on a surface of said drain layer;

a high-resistance semiconductor layer of a first conductivity type formed on a surface of said drain layer, which faces different from said drain electrode;

a base layer of a second conductivity type formed selectively in a surface of said high-resistance semiconductor layer of the first conductivity type, which faces different from said drain layer;

a source layer of the first conductivity type formed selectively in the surface of said base layer of the second conductivity type;

a source electrode formed on said source layer of the first conductivity type and said base layer of the second conductivity type;

a gate electrode in contact with said source layer of the first conductivity type, said base layer of the second conductivity type and said high-resistance semiconductor layer of the first conductivity type through a gate insulating film; and

a buried layer of a second conductivity type selectively formed in said high-resistance semiconductor layer of the first conductivity type, having a floated potential, and extending at substantially right angles to a line connecting said drain and source electrodes and comprising a plurality of strips functioning as current paths, and said plurality of strips are set at a floating potential different from a potential of any other electrode when a depletion layer extending from a region near said drain electrode reaches said buried layer of the second conductivity type.

wherein the following relations hold;

space="preserve" listing-type="equation">Vs=(BV-V.sub.1 -V.sub.2)/(M-1)V;

space="preserve" listing-type="equation">V.sub.1 ≧

Vs;

space="preserve" listing-type="equation">V.sub.2 ≧

Vs;

space="preserve" listing-type="equation">N.sub.1 <

1.897×

10.sup.18 ×

V.sub.1.sup.-1.35 cm.sup.-3 ;

space="preserve" listing-type="equation">N.sub.2 <

1.897×

10.sup.18 ×

V.sub.2.sup.-1.35 cm.sup.-3 ;

space="preserve" listing-type="equation">Ns<

1.897×

10.sup.18 ×

Vs.sup.-1.35 cm.sup.-3 ;

space="preserve" listing-type="equation">W.sub.1 <

1.1247×

10.sup.10 ×

N.sub.1.sup.-0.85 cm;

space="preserve" listing-type="equation">Ws<

1.1247×

10.sup.10 ×

Ns.sup.-0.85 cm; and

where

BV is the breakdown voltage between said source electrode and said drain electrode;

M is the number of said buried layer of the second conductivity type between said source electrode and said drain electrode;

V₁ is the voltage allotted to a first region of said high-resistance semiconductor layer of the first conductivity type between said source electrode and said buried layer of the second conductivity type, said first region being located near said source electrode;

N₁ is the impurities concentration of said first region of said high-resistance semiconductor layer of the first conductivity type;

W₁ is the thickness of said first region of said high-resistance semiconductor layer of the first conductivity type;

V₂ is the voltage allotted to a second region of said high-resistance semiconductor layer of the first conductivity type between said drain electrode and said buried layer of the second conductivity type, said second region being located near said drain electrode;

N₂ is the impurities concentration of said second region of said high-resistance semiconductor layer of the first conductivity type;

Vs is the voltage allotted to a third region of said high-resistance semiconductor layer of the first conductivity type, said third region is between said first and second regions of said high-resistance semiconductor layer of the first conductivity type;

Ns is the impurities concentration of said third region of said high-resistance semiconductor layer of the first conductivity type; and

Ws is the thickness of said third region of said high resistance semiconductor layer of the first conductivity type.