Multiple device test layout

• US 6,037,795 A
• Filed: 09/26/1997
• Issued: 03/14/2000
• Est. Priority Date: 09/26/1997
• Status: Expired due to Term

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Poulin, James J., Raviart, Robert D., Sullivan, Timothy D., Smith, Richard G., Rodbell, Kenneth P., Filippi, Ronald G., Swinton, Alexander J.
• Primary Examiner(s): BROWN, GLENN WARNER
• Application Number:
  US08/938,871
• Time in Patent Office: 900 Days
• Field of Search: 324/760, 324/763, 324/765, 324/158.1
• US Class Current: 324/762.01
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: G01R 31/2858 Measuring of material aspects, e.g. electro-migration [EM], hot carrier injection
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A test layout increases the sample size of electromigration experiments. Through pad sharing, the number of structures tested can be increased, allowing hundreds of identical structures to be tested in a single high temperature oven door.

Claims

1. A test layout for detecting electromigration in conductive interconnects comprising:

a plurality of conductive interconnects, each having at least a first terminal and a second terminal;

an individual I+ pad for receiving a test signal coupled to the first terminal of each of the plurality of conductive interconnects;

at least one common I- pad for receiving the test signal coupled to the second terminal of each of the plurality of conductive interconnects; and

detecting means coupled to at least one of the first and second terminals of each of the plurality of conductive interconnects for detecting electromigration in the plurality of conductive interconnects in response to the test signal.

2. The test layout according to claim 1, wherein the detecting means comprises:

an individual V+ pad coupled to the first terminal of each of the plurality of conductive interconnects; and

at least one common V- pad coupled to the second terminal of each of the plurality of conductive interconnects.

3. The test layout according to claim 1, wherein the detecting means comprises:

at least one monitor adjacent to one of the plurality of conductive interconnects; and

at least one common M pad coupled to the at least one monitor,

wherein leakage current from the one of the plurality of conductive interconnects to the at least one monitor is detected.

4. A test layout according to claim 3, further comprising a substrate, a first metallization layer formed on the substrate, and a second metallization layer formed on the substrate, and

wherein the one of the plurality of conductive interconnects is on one of the first metallization layer and the second metallization layer and the at least one monitor is on one of the first metallization layer and the second metallization layer, and

wherein lateral and vertical extrusion of the one of the plurality of conductive interconnects results in a leakage current from the one of the plurality of conductive interconnects to the at least one monitor.

5. A test layout according to claim 1, wherein each of the plurality of conductive interconnects is one of a single-level and a multi-level interconnection structure on an integrated circuit.

6. A test layout according to claim 1, wherein each of the plurality of conductive interconnects is adapted to fail before any other component of the test layout.

7. A test layout according to claim 1, wherein the test layout is adapted for chip level testing.

8. A test layout according to claim 1, wherein the test layout is adapted for wafer level testing.

9. A test layout according to claim 1, wherein each of the plurality of conductive interconnects is identical.

10. A test layout according to claim 1, wherein each of the plurality of conductive interconnects is different.

11. A test layout according to claim 1, wherein some of the plurality of conductive interconnects are identical and some of the plurality of conductive interconnects are different.

12. A test layout for detecting electromigration comprising:

multi-terminal devices wherein each device is one of a single-level and a multi-level interconnection structure on an integrated circuit, each device having at least a first terminal and a second terminal;

an individual I+ pad coupled to the first terminal of each device;

an individual V+ pad coupled to the first terminal of each device;

at least one common I- pad coupled to the second terminal of each device;

at least one common V- pad coupled to the second terminal of each device;

means for applying a test signal to each device at the I+ and I- pads; and

means for detecting the electromigration of each device at the V+ and V- pads in response to the applied test signal.

13. A test layout according to claim 12, wherein the test layout is adapted for wafer level testing.

14. A test layout according to claim 12, wherein the test layout is adapted for chip level testing.

15. A test layout according to claim 12, wherein each device is adapted to fail before any other component of the test layout.

16. A test layout for detecting metal extrusions of a plurality of devices, each of the plurality of devices including a multi-level conductive interconnect having a first terminal and a second terminal, the test layout comprising:

an individual I+ pad connected by an individual conductor to the first terminal of each device;

an individual V+ pad connected by an individual conductor to the first terminal of each device;

at least one common I- pad connected by conductors to the second terminal of each device;

at least one common V- pad connected by conductors to the second terminal of each device;

at least one monitor adjacent to at least one of the plurality of devices for detecting metal extrusions of the at least one of the plurality of devices;

wherein the conductors are adapted to fail before any other component of the test layout.

17. A method of testing multi-terminal devices each having a respective operating parameter, a first terminal, and a second terminal, the method comprising the steps of:

connecting the first terminal of each one of the multi-terminal devices to an individual I+ pad;

connecting the second terminal of each one of the multi-terminal devices to a common I- pad;

applying a current to each I+ pad; and

detecting a voltage across each one of the multi-terminal devices until the respective operating parameter of each one of the multi-terminal devices exceeds a predetermined limit.

18. A test layout for detecting electromigration comprising:

a plurality of conductive interconnects, each having at least a first terminal and a second terminal;

an individual I+ pad coupled to the first terminal of each of the plurality of conductive interconnects;

at least one common I- pad coupled to the second terminal of each of the plurality of conductive interconnects;

means for applying a test signal to each of the plurality of conductive interconnects at the I+ and I- pads; and

detecting means coupled to at least one of the first and second terminals of each of the plurality of conductive interconnects for detecting electromigration of the plurality of conductive interconnects, the detecting means including an individual V+ pad coupled to the first terminal of each of the plurality of conductive interconnects and at least one common V- pad coupled to the second terminal of each of the plurality of conductive interconnects.

19. A test layout according to claim 18, wherein the plurality of conductive interconnects are adapted to fail before any other component of the test layout by coupling each I+ pad and I- pad to each respective conductive interconnect using a conductor more robust than the respective conductive interconnect.

20. A test layout according to claim 18 further comprising:

at least one extrusion monitor adjacent to one of the plurality of conductive interconnects; and

at least one common M pad coupled to the at least one extrusion monitor for detecting leakage current due to extrusion of the one of the plurality of conductive interconnects.