Signal input circuit

• US 6,037,824 A
• Filed: 10/10/1997
• Issued: 03/14/2000
• Est. Priority Date: 10/13/1996
• Status: Expired due to Term

• Current Assignee: United Microelectronics Corporation
• Original Assignee: Nippon Steel Corporation
• Inventors: Takahashi, Yasuhiko
• Primary Examiner(s): Wells, Kenneth B.
• Application Number:
  US08/948,941
• Time in Patent Office: 886 Days
• Field of Search: 327/100, 327/131, 327/132, 327/336, 327/337, 327/379, 327/551, 327/554, 327/91, 327/94, 327/96
• US Class Current: 327/337
• CPC Class Codes: H03K 5/1252 Suppression or limitation of noise or interference specially adapted for transmission systems H04B15/00, H04L25/08
• CPC Class Codes: H03K 5/22 Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral indicating phase difference of two cyclic pulse trains G01R25/00
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end

Abstract

In a signal input circuit, an input signal integrating circuit integrates an input signal in only a predetermined integration period. A reference voltage integrating circuit integrates a reference voltage in only the predetermined integration period. A differential amplifier circuit amplifies a difference between an output signal of the input signal integrating circuit and an output signal of the reference voltage integrating circuit. The input signal integrating circuit may be a charge/discharge type integrating circuit which stores charges corresponding to the input signal in only the predetermined integration period and thereafter releases the stored charges before the next integration period. The reference voltage integrating circuit may be a charge/discharge type integrating circuit which stores charges corresponding to the reference voltage in only the predetermined integration period and thereafter releases the stored charges before the next integration period. The differential amplifier circuit may be a current mirror type differential amplifier or a cross-coupled sense amplifier.

Claims

1. A signal input circuit comprising:

input signal analog integrating means for integrating an input signal having a noise component in only a predetermined integration period, said input signal integrating means includes an integrating circuit including a charge circuit and a discharge circuit which stores first charges corresponding to said input signal in only said predetermined integration period and thereafter releases the stored first charges before the next integration period;

reference voltage analog integrating means for integrating a reference voltage comprising a substantially constant voltage including a noise component, in only said predetermined integration period, said reference voltage integrating means having an integrating circuit including a charge circuit and a discharge circuit which stores second charges corresponding to said reference voltage in only said predetermined integration period and thereafter releases the stored second charges before the next integration period; and

differential amplifier means for amplifying a difference between an output signal of said input signal analog integrating means and an output signal of said reference voltage analog integrating means, whereby a logic signal is produced based upon the difference between the integrated input signal and the integrated constant voltage signal.

2. A signal input circuit according to claim 1, wherein said differential amplifier means includes a current mirror circuit.

3. A signal input circuit according to claim 1, wherein said differential amplifier means includes a cross-coupled sense amplifier.

4. A signal input circuit according to claim 1, further comprising a reset/set flip-flop circuit which holds an output signal of said differential amplifier means.

5. A signal input circuit comprising first and second signal input circuit units, wherein

said first signal input circuit unit includes:

first input signal analog integrating means for integrating an input signal in only a predetermined integration period at a timing defined by a first clock signal;

first reference voltage analog integrating means for integrating a reference voltage comprising a constant voltage plus noise in only said predetermined integration period at said timing defined by the first clock signal; and

first differential amplifier means for amplifying a difference between an output signal of said first input signal integrating means and an input signal of said first reference voltage integrating means, and

said second signal input circuit unit includes;

second input signal analog integrating means for integrating said input signal in only said predetermined integration period at a timing defined by a second clock signal other than said first clock signal;

second reference voltage analog integrating means for integrating said reference voltage in only said predetermined integration period at said timing defined by the second clock signal; and

second differential amplifier means for amplifying a difference between an output signal of said second input signal integrating means and an output signal of said second reference voltage integrating means.

6. A signal input circuit according to claim 5, wherein

said first input signal integrating means includes an integrating circuit including a charge circuit and a discharge circuit which stores first charges corresponding to said input signal in only said predetermined integration period and thereafter releases the stored first charges before the next integration period,

said first reference voltage integrating means includes an integrating circuit including a charge circuit and a discharge circuit which stores second charges corresponding to said reference voltage in only said predetermined integration period and thereafter releases the stored second charges before the next integration period,

said second input signal integrating means includes an integrating circuit including a charge circuit and a discharge circuit which stores third charges corresponding to said input signal in only said predetermined integration period and thereafter releases the stored third charges before the next integration period, and

said second reference voltage integrating means includes an integrating circuit including a charge circuit and a discharge circuit which stores fourth charges corresponding to said reference voltage in only said predetermined integration period and thereafter releases the stored fourth charges before the next integration period.

7. A signal input circuit according to claim 5, wherein each of said first and second differential amplifier means includes a current mirror type differential amplifier.

8. A signal input circuit according to claim 5, wherein each of said first and second differential amplifier means includes a cross-coupled sense amplifier.

9. A signal input circuit according to claim 5, further comprising:

a first reset/set flip-flop circuit which holds an output signal of said first differential amplifier means; and

a second reset/set flip-flop circuit which holds an output signal of said second differential amplifier.

10. A signal input circuit comprising an integrating circuit section, a change-over section and a differential-amplifier/latch section, wherein

said integrating circuit section includes:

a charging portion provided with a first charging transistor which has a gate inputted with an input signal and a drain connected to a first integrating node and a second charging transistor which has a gate inputted with a reference voltage and a drain connected to a second integrating node; and

a first discharging portion for setting each of a voltage of said first integrating node and a voltage of said second integrating node to a predetermined voltage inclusive of 0 V in accordance with a first clock signal,

said change-over section includes;

a first separating transistor having a source/drain connected to said first integrating node and a drain/source connected to a first node, said first separating transistor being turned on in accordance with said first clock signal;

a second separating transistor having a source/drain connected to said second integrating node and a drain/source connected to a second node, said second separating transistor being turned on simultaneously with said first separating transistor in accordance with said first clock signal;

a third separating transistor having a source/drain connected to said first node and a drain/source connected to a third node, said third separating transistor being turned on when said first separating transistor is turned off in accordance with said first clock signal; and

a fourth separating transistor having a source/drain connected to said second node and a drain/source connected to a fourth node, said fourth separating transistor being turned on simultaneously with said third separating transistor in accordance with said first clock signal, and

said differential-amplifier/latch section includes;

a sense amplifier portion provided with a first inverter circuit which has an input terminal connected to said second node and an output terminal connected to said third node and a second inverter circuit which has an input terminal connected to said first node and an output terminal connected to said fourth node, said sense amplifier portion amplifying a difference between a voltage of said first node and a voltage of said second node in accordance with a logical product of said first clock signal and a second clock signal different in phase from said first clock signal;

a second discharging portion for setting each of a voltage of said third node and a voltage of said fourth node to a predetermined voltage inclusive of 0 V in accordance with a third clock signal; and

a latch portion provided with a reset/set flip-flop circuit inputted with the voltage of said third node and the voltage of said fourth node.