Complementary metal-oxide semiconductor voltage controlled oscillator (CMOS VCO)

• US 6,037,842 A
• Filed: 04/21/1998
• Issued: 03/14/2000
• Est. Priority Date: 04/21/1998
• Status: Expired due to Term

• Current Assignee: MACOM Connectivity Solutions, LLC (MACOM Technology Solutions Holdings, Inc.)
• Original Assignee: Applied Micro Circuits Corporation (MACOM Technology Solutions Holdings, Inc.)
• Inventors: Bryan, Thomas Clark, Merrill, Allen Carl
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US09/063,526
• Time in Patent Office: 693 Days
• Field of Search: 331/57, 331/34, 331/177 R, 331/46, 331/48, 331/111, 331/108 C, 331/143, 327/280, 327/281, 327/274, 327/287, 327/288
• US Class Current: 331/57
• CPC Class Codes: H03K 3/0231 Astable circuits H03K3/0315 takes precedence
• CPC Class Codes: H03K 3/354 Astable circuits

Abstract

An integrated circuit complementary metal-oxide silicon (CMOS) voltage controlled oscillator (VCO) includes a plurality of variable delay elements, connected in a ring configuration, each variable delay element including a pair of parallel connected differential CMOS sections. The parallel-connected differential CMOS sections of each variable delay element are controlled by a differential control voltage whose magnitude sets relative levels of operation of the two differential sections of each variable delay element. These relative levels of operation determine the delay through the variable delay element. A current mirror circuit provides the differential control voltage.

Claims

1. A complementary metal-oxide semiconductor (CMOS) voltage controlled oscillator (VCO) comprising:

a control means for producing a differential control signal; and

a plurality of variable delay elements connected in a ring configuration;

each variable delay element including first and second differential amplifier sections connected in parallel, each differential amplifier section including at least two CMOS transistors connected in a differential configuration, and a CMOS transistor current source connected to the at least two CMOS transistors and to the control means for operating the each differential amplifier section in response to a differential control signal, the first differential amplifier section having a first delay and second differential amplifier section having a second delay, the second delay being less than the first delay.

2. The CMOS VCO of claim 1, wherein delay through each variable delay element is determined by a degree of operation of the first differential section and a degree of operation of the second differential section.

3. The CMOS VCO of claim 2, each CMOS transistor being characterized by a ratio W/L, where W is a gate width and L is a gate length, wherein W/L of the two CMOS transistors in the first differential section is less than W/L of the two CMOS transistors in the second section.

4. The CMOS VCO of claim 1, each CMOS transistor being characterized by a ratio W/L, where W is a gate width and L is a gate length, wherein W/L of the two CMOS transistors in the first differential section is less than W/L of the two CMOS transistors in the second section.

5. The CMOS VCO of claim 1, each CMOS transistor current source including a CMOS transistor characterized by a ratio W/L, where W is a gate width and L is a gate length, wherein W/L of the CMOS transistor in the first differential section is less than W/L of the CMOS transistor in the second differential section.

6. The CMOS of claim 2, each CMOS transistor current source including a CMOS transistor characterized by a ratio W/L, where W is a gate width and L is a gate length, wherein W/L of the CMOS transistor in the first differential section is less than W/L of the CMOS transistor in the second differential section.

7. The CMOS VCO of claim 6, each CMOS transistor being characterized by a ratio W/L, where W is a gate width and L is a gate length, wherein W/L of the two CMOS transistors in the first differential section is less than W/L of the two CMOS transistors in the second section.

8. The CMOS VCO of claim 1, wherein the differential control signal has two components and the control means includes two CMOS transistor current mirrors, each for providing a respective component of the differential control signal.

9. The CMOS VCO of claim 8, wherein delay through each variable delay element is determined by a composite of the degrees of operation of the first differential section and the second differential section, the degrees of operation being established by the components of the differential control signal.

10. The CMOS VCO of claim 1, wherein each differential amplifier section has a maximum frequency of operation, the maximum frequency of operation of the first differential section being about 700 MHz and the maximum frequency of operation of the second section being about 1.8 GHz.

11. A monolithic complementary metal-oxide semiconductor (CMOS) integrated circuit (IC), comprising:

a plurality of circuits; and

at least one voltage-controlled oscillator (VCO) that includes;

a plurality of variable delay elements connected in a ring configuration;

each variable delay element including first and second differential amplifier sections connected in parallel, each differential amplifier section including at least two CMOS transistors connected in a differential configurations and a CMOS transistor current source connected to the at least two CMOS transistors and to the control means for operating each differential amplifier section in response to a differential control signal, the first differential amplifier section having a first delay and the second differential amplifier section having a second delay, the second delay being less than the first delay.

12. The IC device of claim 11, wherein delay through each variable delay element is determined by a degree of operation of the first differential section and a degree of operation of the second differential section.

13. The IC device of claim 12, each CMOS transistor being characterized by a ratio W/L, where W is a gate width and L is a gate length, wherein W/L of the two CMOS transistors in the first differential section is less than W/L of the two CMOS transistors in the second section.

14. The IC device of claim 11, each CMOS transistor being characterized by a ratio W/L, where W is a gate width and L is a gate length, wherein W/L of the two CMOS transistors in the first differential section is less than W/L of the two CMOS transistors in the second section.

15. The IC device of claim 11, each CMOS transistor current source including a CMOS transistor characterized by a ratio W/L, where W is a gate width and L is a gate length, wherein W/L of the CMOS transistor in the first differential section is less than W/L of the CMOS transistor in the second differential section.

16. The IC device of claim 12, each CMOS transistor current source including a CMOS transistor characterized by a ratio W/L, where W is a gate width and L is a gate length, wherein W/L of the CMOS transistor in the first differential section is less than W/L of the CMOS transistor in the second differential section.

17. The IC device of claim 16, each CMOS transistor being characterized by a ratio W/L, where W is a gate width and L is a gate length, wherein W/L of the two CMOS transistors in the first differential section is less than W/L of the two CMOS transistors in the second section.

18. The IC device of claim 11, wherein the differential control signal has two components and the control means includes two CMOS transistor current mirrors, each for providing a respective component of the differential control signal.

19. The IC device of claim 18, wherein delay through each variable delay element is determined by a composite of the degrees of operation of the first differential section and the second differential section, the degrees of operation being established by the components of the differential control signal.

20. The IC device of claim 11, wherein each differential amplifier section has a maximum frequency of operation, the maximum frequency of operation of the first differential section being about 700 MHz and the maximum frequency of operation of the second section being about 1.8 GHz.