Single ended read scheme with segmented bitline of multi-port register file

• US 6,038,193 A
• Filed: 12/23/1998
• Issued: 03/14/2000
• Est. Priority Date: 12/23/1998
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Wang, Yong, Kant, Shree
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US09/221,001
• Time in Patent Office: 447 Days
• Field of Search: 365/189.04, 365/189.01, 365/230.03, 365/230.05
• US Class Current: 365/230.05
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/067 Single-ended amplifiers
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A read system for a multi-ported register file includes a segmented bit line coupled to a global bit line. Each local bit line segment is coupled to a sub-set of the register files in a column to reduce device load and connection load. The local bit line segments are each coupled in series by local sense amps with the local bit line segment coupled to the input of a global sense amplifier. The number of cells coupled to the last bit line segment is more than the number of cells coupled to a bit line segment farthest from the global sense amplifier to balance device and interconnect load and provide for uniform read timing. Both the local bit line segments and global bit line are precharged prior to sensing a bit so that the local sense amplifiers do not require output pull-up transistors. This scheme will not work if the local sense amp includes a pull-up PMOS transistor at its output.

Claims

1. A system for reading data from a multi-ported register file of the type including an array of rows and columns of register file cells, which each port of a register file in one of the rows coupled to a bit line, said system comprising:

a first plurality of bit line segments, each coupled to a subgroup of the rows of register file cells in the array, with each subgroup including a designated number of register file cells;

a second plurality, being one less than the first plurality, of local sense amplifiers, each local sense amp having an input coupled to a respective preceding local bit line segment and an output coupled to a following local bit line segment to coupled said bit line segments in series, with each local sense amplifier having a precharge circuit of precharging the preceding local bit line prior to sensing a bit read from a register file cell in the array coupled to the bit line segment, and having an output port for providing a output signal determined by the value of a sensed bit;

a global sense amp, having an input coupled to a last local bit line segment line and having a precharge circuit for precharging the last bit line segment prior to sensing a signal on the last local bit line segment, with the designated number of register files cells connected to the last bit line segment being less than the designated number of register file cells connected to another of the bit line segments.

2. The system of claim 1 where said local sense amp further comprises:

an inverter, having an input connected to the local bit line segment, and an output;

a first pull-down transistor, having a gate connected to the output of the inverter, a drain connected to the global bit line, and a source;

a second pull-down transistor, having a gate connected to the precharge circuit, a drain connected to the source of the first pull-down transistor, and a source connected to ground so that signal delay of the inverter will not cause the first pull-down transistor to pull down the global bit line when it is being precharged.

3. The system of claim 1 where said local sense amp further comprises:

a feedback inverter, coupling the output of the skewed inverter to the local bit line segment to restore the value of the bit line by providing a leakage current to the bit line.

4. The system of claim 2 wherein said inverter has a trip point skewed towards the supply voltage to more quickly sense a falling input signal.