Combined signalling and PCM cross-connect and packet engine

• US 6,038,226 A
• Filed: 03/31/1997
• Issued: 03/14/2000
• Est. Priority Date: 03/31/1997
• Status: Expired due to Term

• Current Assignee: Ericsson, Inc. (Telefonaktiebolaget LM Ericsson)
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Ellersick, William F., Falcomato, Rocco, Saneski, Steven Philip
• Primary Examiner(s): Hofsass, Jeffery A.
• Assistant Examiner(s): TOWNSEND, CLEMENT G
• Application Number:
  US08/828,576
• Time in Patent Office: 1,079 Days
• Field of Search: 370/352, 370/375, 370/466, 370/467, 370/522, 370/523
• US Class Current: 370/352
• CPC Class Codes: H04Q 11/04 for time-division multiplexing H04Q11/0001 takes precedence

Abstract

A combined signalling and PCM cross-connect and packet assembly/disassembly engine includes a cross-connect memory, wherein the memory advantageously includes both a subscriber PCM channel memory that cross-connects bus side PCM channels to optical fiber timeslots, and a separate signalling memory that cross-connects associated signalling data channels to optical fiber timeslots. In particular, the PCM and signalling data memories are substantially the same size and each signalling data channel is mapped to an address in the signalling memory that corresponds to the PCM memory address of the associated PCM channel. Cross-connect information used for the PCM channels is also used to cross-connect the associated signalling channels. Cross-connect and packet engine functions are combined, thereby eliminating the need for a separate buffer to accommodate differences in transmission rates between them. A single control store with an associated fiber timeslot counter is also connected to the packet engine circuit, which supports both PCM and signalling data channels.

Claims

1. A circuit configured to cross-connect data carried in PCM and associated signalling channels of a first side data stream into PCM and associated signalling channels of a second side data stream, wherein the first side PCM channels are received in successive time division multiplexed data frames and the first side signalling channels are received over signalling multiframes comprising a plurality of successive data frames, the cross-connect circuit comprising:

a PCM memory configured to store data carried in first side PCM channels of each data frame at an address corresponding to the respective data frame timeslot in which the PCM channel is received; and

a signalling memory configured to store data carried in the first side signalling channels of each signalling multiframe at an address corresponding to the data frame timeslot of its associated PCM channel, wherein the PCM and signalling memories may be configured to be substantially the same size.

2. The cross-connect circuit of claim 1, further comprising a programmable cross-connect control store configured to read data stored in the PCM and signalling memories and transmit them in respective assigned second side PCM and signalling channels.

3. The cross-connect circuit of claim 2, wherein the respective PCM memory and control store are configured such that PCM data for first side PCM channels is stored in the PCM memory for each data frame and is read into the respective assigned second side PCM channels during the ensuing data frame.

4. The cross-connect circuit of claim 3, wherein the respective signalling memory and control store are configured such that signalling data associated with the first side PCM channels is stored in the signalling memory for each signalling multiframe and is read into the respective assigned second side signalling channels during the ensuing signalling multiframe.

5. The cross-connect circuit of claim 1, further comprising

means for determining whether received first side data channels in each timeslot of each successive data frame of a signalling multiframe are carrying signalling data, and

means for supplying an address to the signalling memory if signalling data is carried in a respective received timeslot, the address corresponding to the data frame timeslot of an associated first side PCM channel.

6. The cross-connect circuit of claim 5, wherein the means for determining whether the received first side data for each timeslot is signalling data comprise a first side control store that receives as an input the timeslot number of the received data channel and performs a look up operation of first side signalling channel assignments.

7. The cross-connect circuit of claim 6, wherein the means for supplying an address to the signalling memory if signalling data is carried in a respective received timeslot comprise a circuit that computes the timeslot number of the first side PCM channel associated with the signalling data based on the respective signalling frame and timeslot numbers of the received data channel and the result of the look up operation performed by the first side control store, the signalling frame number being initialized at the beginning of each new signalling multiframe and incremented with each first side data frame within the signalling multiframe.

8. The cross-connect circuit of claim 1, further comprising means for assembling the second side data stream into data packets.

9. The cross-connect circuit of claim 1, further comprising a first side timeslot counter that outputs a successive timeslot number of a second side data frame for each received data channel of a first side data frame, wherein the timeslot numbers are repeated for each successively received first side data frame.

10. A circuit configured to cross-connect data carried in incoming first side PCM and associated signalling channels into outgoing second side PCM and associated signalling channels, and to cross-connect data carried in incoming second side PCM and associated signalling channels into outgoing first side PCM and associated signalling channels, wherein the incoming first side PCM channels are received in successive time division multiplexed first side data frames and the incoming first side signalling channels are received over signalling multiframes comprising a plurality of successive first side data frames, the cross-connect circuit comprising:

a first PCM memory configured to store data carried in PCM channels of each incoming first side data frame at an address corresponding to the respective first side data frame timeslot in which the PCM channel is received; and

a first signalling memory configured to store data carried in the incoming first side signalling channels of each signalling multiframe at an address corresponding to the first side data frame timeslot of its associated PCM channel.

11. The cross-connect circuit of claim 10, wherein the incoming second side PCM channels are received in successive time division multiplexed second side data frames and the incoming second side signalling channels are received over signalling multiframes comprising a plurality of successive second side data frames, further comprising

a second PCM memory configured to store data carried in the PCM channels of each incoming second side data frame at an address corresponding to respective assigned first side data frame timeslots;

and

a second signalling memory configured to store data carried in the second side signalling channels of each signalling multiframe at an address corresponding to respective first side data frame timeslots to which the data carried in their associated PCM channels is assigned.

12. The cross-connect of claim 11, wherein incoming and outgoing first side data frames are transmitted at the same frame rate as the incoming and outgoing second side data frames.

13. The cross-connect of claim 12, wherein incoming and outgoing first side data frames are transmitted at a higher bit rate than the incoming and outgoing second side data frames.

14. The cross-connect circuit of claim 11, further comprising a programmable cross-connect control store configured to read data stored in the first PCM and signalling memories into respective assigned outgoing second side PCM and signalling channels, and to read data stored in the second PCM and signalling memories into respective assigned outgoing first side PCM and signalling channels.

15. The cross-connect circuit of claim 10, further comprising

means for assembling the outgoing second side data frames into data packets configured for asynchronous transmission, and

means for disassembling received data packets into incoming second side data frames.

16. A circuit configured to cross-connect data carried in first side downstream PCM and signalling channels into second side downstream PCM and signalling channels, and to cross-connect data carried in second side upstream PCM and signalling channels into first side upstream PCM and signalling channels, wherein the first side downstream and upstream PCM channels are received and transmitted, respectively, in successive first side data frames, the first side downstream and upstream signalling channels associated with the first side downstream and upstream PCM channels being received and transmitted, respectively, over signalling multiframes comprising a plurality of successive first side data frames, and wherein the second side downstream and upstream PCM channels are received and transmitted, respectively, in successive second side data frames, the second side downstream and upstream signalling channels associated with the second side downstream and upstream PCM channels being received and transmitted, respectively, over signalling multiframes comprising a plurality of successive second side data frames, the cross-connect circuit comprising:

a first memory having a first portion configured to store data carried in the first side downstream PCM channels at an address corresponding to the first side data frame timeslot in which the PCM data is received, and a second portion configured to store data contained in the first side downstream signalling channels at an address corresponding to the respective first side data frame timeslot of their associated PCM channels; and

a second memory having a first portion configured to store data carried in the second side upstream PCM channels at an address corresponding to the first side data frame timeslot in which the PCM data is assigned, and a second portion configured to store data contained in the second side upstream signalling channels at an address corresponding to the respective first side data frame timeslot assigned to their associated PCM channels.

17. The cross-connect circuit of claim 16, further comprising

means for determining whether received first side data channels in each timeslot of each successive data frame of a signalling multiframe are carrying signalling data, and

means for supplying an address to the signalling memory if signalling data is carried in a respective received timeslot, the address corresponding to the data frame timeslot of an associated first side PCM channel.

18. The cross-connect circuit of claim 17, wherein the means for determining whether the received first side data for each timeslot is signalling data comprise a first side control store that receives as an input the timeslot number of the received data channel and performs a look up operation of first side signalling channel assignments.

19. The cross-connect circuit of claim 18, wherein the means for supplying an address to the signalling memory if signalling data is carried in a respective received timeslot comprise a circuit that computes the timeslot number of the first side PCM channel associated with the signalling data based on the respective signalling frame and timeslot numbers of the received data channel and the result of the look up operation performed by the first side control store, the signalling frame number being initialized at the beginning of each new signalling multiframe and incremented with each first side data frame within the signalling multiframe.

20. The circuit of claim 18, further comprising means for assembling the second side downstream data frames into downstream data packets, and

means for disassembling received upstream packets into second side upstream data frames.