Data pipeline system and data encoding method

• US 6,038,380 A
• Filed: 07/31/1997
• Issued: 03/14/2000
• Est. Priority Date: 06/30/1992
• Status: Expired due to Term

• Current Assignee: Coases Investments Bros LLC (Intellectual Ventures LLC)
• Original Assignee: Discovision Associates (Pioneer Corporation)
• Inventors: Wise, Adrian Philip, Robbins, William Philip, Sotheran, Martin William
• Primary Examiner(s): Bowler, Alyssa H.
• Assistant Examiner(s): Davis, Jr., Walter D.
• Application Number:
  US08/903,969
• Time in Patent Office: 957 Days
• Field of Search: 395/376, 345/501, 382/246
• US Class Current: 712/200
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/4494 data driven
• CPC Class Codes: H04N 19/13 Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/44 Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/91 Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Abstract

A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Claims

1. In a pipeline machine, comprising a plurality of processing stages, the improvement characterized by:

two successive ones of said processing stages being connected by a two-wire link, wherein said two-wire link comprises;

a sender, a receiver, and a clock connected to said sender and said receiver, wherein data is transferred from said sender to said receiver upon a transition of said clock only when said sender is ready and said receiver is ready;

wherein variable length tokens having data and control functions propagate across said two-wire link, said tokens each comprising a plurality of data words, each said word including an extension bit which indicates a presence or an absence of additional words in said token, a length of said token being determined by said extension bits;

whereby said tokens are unlimited in length;

said processing stages comprising a spatial decoder accepting an encoded data stream having a plurality of video formats carried therein, said formats including at least an MPEG format;

a DRAM interface in said spatial decoder having a plurality of data buffers therein, and a RAM accepting data from said DRAM interface;

a coded data buffer;

a token generator, generating variable length tokens, a said variable length token comprising a PICTURE_-- END token and a FLUSH token;

means responsive to said PICTURE_-- END token for performing a stop-after-picture operation for achieving a clear end to picture data decoding, for indicating the end of a picture, and for clearing the pipeline;

wherein responsive to said PICTURE_-- END token, data is cleared from said data buffers of said DRAM interface, and data in said coded data buffer is presented to a Huffman decoder of said spatial decoder, and responsive to said FLUSH token a portion of said processing stages are reconfigured to await arrival of further data.

2. The machine according to claim 1, wherein at least one of said processing stages has a variable length DATA token stored therein, and responsive to said PICTURE_-- END token, said one processing stage adds bits to a last word of said DATA token until said DATA token is padded to a predetermined size.

3. The machine according to claim 2, wherein responsive to said FLUSH token registers of said processing stages are reset to stand-by condition, and a STOP_-- AFTER_-- PICTURE state is established, wherein input to said processing stages is not accepted.

4. The machine according to claim 2, wherein a padded DATA token is written to said coded data buffer.

5. The machine according to claim 1, wherein said data buffers of said DRAM interface comprise a swing buffer.

6. The machine according to claim 5, further comprising:

a buffer manager for allocating buffers of said swing buffer;

a zero_-- buffer register in said DRAM interface;

wherein responsive to a condition of said zero_-- buffer register, an output of said buffer manager is ignored, whereby said data buffers of said DRAM are by-passed by data passing through said DRAM interface.

7. The machine according to claim 1, wherein responsive to a picture end point in said data stream, a last word of a variable length DATA token is padded by said token generator and written to said coded data buffer.