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Method for controlling power and slew in a programmable logic device

  • US 6,038,386 A
  • Filed: 08/21/1997
  • Issued: 03/14/2000
  • Est. Priority Date: 08/21/1997
  • Status: Expired due to Term
First Claim
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1. A method for controlling power consumption of a programmable logic device, the programmable logic device including a plurality of resources that are programmable to implement a user-defined logic function, each resource being programmable to operate in either a high power mode or a low power mode, the method comprising the steps of:

  • placing and routing the user-defined logic function such that a plurality of paths of the logic function are assigned to associated resources of the programmable logic device;

    identifying a group of said resources associated with at least one path of the logic function which is constrained by a user-defined timing specification;

    identifying a sub-group of resources from said group which, when operated in the low power mode, minimizes power consumption of the programmable logic device while satisfying the user-defined timing specifications of said at least one path; and

    setting the plurality of resources such that the sub-group of resources operate in the low power mode, and a remainder of said resources of the group operate in the high power mode.

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