Method for controlling power and slew in a programmable logic device

• US 6,038,386 A
• Filed: 08/21/1997
• Issued: 03/14/2000
• Est. Priority Date: 08/21/1997
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Jain, Gitu
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Kik, Phallaka
• Application Number:
  US08/918,731
• Time in Patent Office: 936 Days
• Field of Search: 364/488-491, 364/578, 395/500.02-500.19
• US Class Current: 716/113
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A method for controlling power consumption and output slew rate in a programmable logic device, which is programmable to emulate a user-defined logic function. After placing and routing the user-defined logic function such that a plurality of paths are assigned to associated resources of the programmable logic device, a group of the resources associated with at least one path of the logic function which is constrained by a user-defined timing specification is identified. These resources are sorted according to their respective power consumption. A first sub-group of the resources is then identified which, when operated in a low power mode, minimizes power consumption of the programmable logic device while satisfying the user-defined timing specifications of all paths. Also, a second sub-group of the resources is identified which, when operated in a slow slew mode, minimizes noise at the output terminals of the programmable logic device while satisfying the user-defined timing specifications of all paths ending at that output terminal. A target PLD is then programmed in accordance with the placement arrangement, and the resources of the first and second groups are set to low power mode and slow slew mode, respectively.

Claims

1. A method for controlling power consumption of a programmable logic device, the programmable logic device including a plurality of resources that are programmable to implement a user-defined logic function, each resource being programmable to operate in either a high power mode or a low power mode, the method comprising the steps of:

placing and routing the user-defined logic function such that a plurality of paths of the logic function are assigned to associated resources of the programmable logic device;

identifying a group of said resources associated with at least one path of the logic function which is constrained by a user-defined timing specification;

identifying a sub-group of resources from said group which, when operated in the low power mode, minimizes power consumption of the programmable logic device while satisfying the user-defined timing specifications of said at least one path; and

setting the plurality of resources such that the sub-group of resources operate in the low power mode, and a remainder of said resources of the group operate in the high power mode.

2. The method according to claim 1, wherein the step of identifying the sub-group further comprises forming a set of combinations of resources from the group which satisfy the user-defined timing specifications in the low power mode, and identifying a combination from the set of combinations which produces the smallest power consumption.

3. The method according to claim 1, wherein the step of identifying a sub-group of resources comprises:

forming a plurality of constraint equations, each constraint equation being associated with one path of the logic function, each constraint equation including a set of variables representing each resource of its associated path and a value representing a maximum number of resources in the associated path that can be operated in the low power mode without violating the timing specification assigned to the associated path;

forming an objective function including a sum of N variables, each of the N variables being associated with one of the resources in the group of resources, each variable being multiplied by a coefficient whose value corresponds to an amount of power consumed by said associated one of the resources; and

selecting the sub-group of resources which maximizes the objective function while satisfying all of the constraint equations.

4. The method according to claim 3, wherein the step of selecting the sub-group of resources comprises utilizing an integer programming solver.

5. The method according to claim 4, wherein the step of utilizing the integer programming solver comprises:

adding a selected resource to the sub-group;

propagating constraints generated by adding the selected resource in each of the constraint equations; and

determining whether the addition of the selected resource to the sub-group violates any of the constraint equations.

6. The method according to claim 5, further comprising the steps of:

setting all of the variables of the objective function to zero before the step of adding the selected resource to the sub-group; and

determining whether all resources of the group have either been added to the sub-group, or eliminated from the sub-group during the step of propagating constraints.

7. The method according to claim 5, wherein the step of adding a selected resource to the sub-group further comprises assigning a value of one to the constraint equation variables associated with the selected resource such that each constraint equation corresponding to a path including the selected resource is increased by one.

8. The method according to claim 7, wherein the step of propagating constraints further comprises comparing each constraint equation with its associated value representing the maximum number of resources that can be operated in the low power mode, and temporarily assigning a value of zero to all variables associated with resources in each constraint equation whose sum of variables is equal to its associated value.

9. The method according to claim 8, further comprising the steps of:

removing the selected resource from the sub-group and assigning a value of zero to all variables in the constraint equations associated with the selected resource if the step of determining identifies a constraint equation which is violated by the addition of the selected resource to the sub-group; and

repeating the step of propagating constraints.

10. The method according to claim 9, further comprising the steps of:

setting all of the variables of the objective function to zero before the step of adding the selected resource to the sub-group; and

determining whether all of the variables in the objective function have been assigned a value in any of the steps of adding the selected resource, removing the selected resource, or propagating constraints; and

if all variables have been assigned a value, storing the sum of N variables from the objective function.

11. A method for controlling an output slew rate of a programmable logic device, the programmable logic device including a plurality of resources that are programmable to implement a user-defined logic function, each resource being programmable to operate in either a fast slew mode or a slow slew mode, the method comprising the steps of:

placing and routing the user-defined logic function such that a plurality of signal paths of the logic function are assigned to associated resources of the programmable logic device;

identifying a group of said resources associated with at least one path of the logic function which is constrained by a user-defined timing specification;

identifying a sub-group of resources from said group which, when operated in the slow slew mode, minimizes noise at the output terminals of the programmable logic device while satisfying the user-defined timing specifications of said at least one path; and

setting the plurality of resources such that the sub-group of resources operate in the slow slew mode, and a remainder of said resources of the group operate in the fast slew mode.

12. The method according to claim 11, wherein the step of identifying the sub-group further comprises selecting a path from the plurality of paths which terminates at an output node, and determining whether the output node of the selected path is designated for fast slew mode operation.

13. The method according to claim 12, wherein the step of identifying the sub-group further comprises:

identifying all paths ending at the output node;

comparing the slacks associated with the selected path and the identified paths with a predetermined additional delay produced when the output node is operated in the slow slew mode; and

designating the output node for slow slew mode operation if the slacks of the selected path and the identified paths are greater than or equal to the predetermined additional delay.

14. A method for controlling power consumption and an output slew rate of a programmable logic device, the complex programmable logic device including a plurality of resources that are programmable to emulate a user-defined logic function, each resource being programmable to operate in either a high power mode or a low power mode, each resource also being programmable to operate in either a fast slew mode or a slow slew mode, the method comprising the steps of:

placing the user-defined logic function such that a plurality of paths of the logic function are assigned to associated resources of the programmable logic device;

identifying a group of said resources associated with at least one path of the logic function which is constrained by a user-defined timing specification;

identifying at least one of a first sub-group and a second sub-group of resources from said group, wherein the first sub-group, when operated in the low power mode, minimizes power consumption of the programmable logic device while satisfying the user-defined timing specifications of said at least one path, and wherein the second sub-group, when operated in the slow slew mode, minimizes noise at the output terminals of the programmable logic device while satisfying the user-defined timing specifications of said at least one path; and

setting the plurality of resources such that the first sub-group of resources operate in the low power mode, and the second sub-group of resources of the group operate in the slow slew mode.

15. The method according to claim 14, wherein said first sub-group is identified before said second sub-group.

16. The method according to claim 14, wherein said second sub-group is identified before said first sub-group.

17. The method according to claim 14, wherein the first sub-group of resources comprise macrocells of the programmable logic device, and the second sub-group of resources comprise output modules of the programmable logic device.

18. The method of claim 17, wherein the step of identifying further comprises the steps of:

forming a plurality of constraint equations, each constraint equation being associated with one path of the logic function, each constraint equation including a set of variables representing each macrocell of its associated path and a value representing a maximum number of macrocells in the associated path that can be operated in the low power mode without violating the timing specification assigned to the associated path;

forming an objective function including a sum of N variables, each of the N variables being associated with one of the macrocells in the group of resources, each variable being multiplied by a coefficient whose value is equal to a number of product terms assigned to the macrocell; and

selecting said first sub-group of macrocells which maximizes the objective function while satisfying all of the constraint equations.

19. The method according to claim 18, wherein the step of selecting the first sub-group comprises:

adding a selected macrocell to the first sub-group;

propagating constraints generated by adding the selected macrocell in each of the constraint equations; and

determining whether the addition of the selected macrocell to the sub-group violates any of the constraint equations.

20. The method according to claim 17, wherein the step of identifying further comprises the steps of:

selecting a path from the plurality of paths which terminates at an output module;

identifying all paths ending at the output module;

comparing the slacks associated with the selected path and the identified paths with a predetermined additional delay resulting from operating the output module in the slow slew mode; and

designating the output module for slow slew mode operation if the slacks of the selected path and the identified paths are greater than or equal to the predetermined additional delay.