Compiling apparatus and method for a VLIW system computer and a recording medium for storing compile execution programs

• US 6,038,396 A
• Filed: 03/17/1998
• Issued: 03/14/2000
• Est. Priority Date: 10/29/1997
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Iwata, Yasushi, Asato, Akira
• Primary Examiner(s): Hafiz, Tariq R.
• Assistant Examiner(s): ZHEN, WEI Y
• Application Number:
  US09/042,799
• Time in Patent Office: 728 Days
• Field of Search: 395/706
• US Class Current: 717/161
• CPC Class Codes: G06F 8/445 Exploiting fine grain parallelism, i.e. parallelism at instruction level run-time instruction scheduling G06F9/3836
• CPC Class Codes: G06F 8/447 Target code generation

Abstract

A compiling apparatus and method, and a recording medium, are used to facilitate assembly code programming of a VLIW computer system. An instruction of an intermediate code format, designated for each slot of the VLIW instruction, is divided corresponding to each slot and stored into a plurality of intermediate code files. The instructions of the intermediate code format stored in the intermediate code files are then read in serially to execute an instruction scheduling process, taking into account dependency between instructions. The serialized instructions of the intermediate code format are converted into parallel assembly code, and an object program of the parallel assembly code is output.

Claims

1. A compiling apparatus compiling an instruction stream executable by a VLIW system computer, said VLIW system computer executing in parallel instruction elements of a VLIW instruction, said compiling apparatus comprising:

at least one intermediate code file dividing and storing instructions of intermediate code format for each slot of the VLIW instruction based on the each slot;

a serializing processing unit serializing and reading the instructions of the intermediate code format which have been divided and stored as the plurality of intermediate code files;

an instruction scheduling unit registering a number, corresponding to each serialized instruction of the intermediate code format, to a resource reservation table;

a paralleled assembly code converting unit converting the serialized instruction of the intermediate code format into parallel assembly code based on the instruction number in the resource reservation table produced by the instruction scheduling unit; and

a paralleled assembly code output unit outputting an object program of the parallel assembly code converted by the paralleled assembly code converting unit.

2. The compiling apparatus according to claim 1, wherein the intermediate code file does not include an NOP instruction.

3. The compiling apparatus according to claim 2, wherein an NOP instruction is inserted in the paralleled assembly code converting unit.

4. The compiling apparatus according to claim 1, wherein the each slot is defined by a plurality of slots which is less than the total number of slots of the VLIW instruction, and an instruction of the intermediate code format for each slot is located in at least one intermediate code file.

5. The compiling apparatus according to claim 1, wherein control information, specifying timing for using a common resource between instructions for different intermediate code files, is located in an intermediate code file.

6. A compiling method compiling an instruction stream to be executed by a VLIW system computer, said VLIW system computer executing in parallel each instruction element of a VLIW instruction, said method comprising the steps of:

a process dividing instructions having an intermediate code format into each slot of the VLIW instruction, and storing the divided instructions to a plurality of intermediate code files;

a serializing process serializing and reading the instructions of the intermediate code format stored in the plurality of intermediate code files;

an instruction scheduling process registering a number, corresponding to each serialized instruction of the intermediate code format, to a writing area of a resource reservation table to produce the resource reservation table;

a paralleled assembly code converting process converting the serialized instructions of the intermediate code format to parallel assembly code depending on an instruction number in the resource reservation table produced in the instruction scheduling process step; and

a paralleled assembly code output process outputting an object program of the parallel assembly code converted by the paralleled assembly code converting process.

7. The compiling method according to claim 6, wherein the intermediate code file does not include an NOP instruction.

8. A compiling method according to claim 7, wherein the converting step further comprises inserting an NOP instruction.

9. The compiling method according to claim 6, further comprising the step of defining the slots as a plurality of slots which is less than the total number of slots of the VLIW instruction, and locating the instruction of the intermediate code format for each slot into at least one intermediate code file.

10. The compiling method according to claim 6, further comprising the step of specifying in the intermediate code file control information for use in specifying the timing of a common resource used by the instructions of different intermediate code files.

11. A recording medium, readable by a computer, storing a compile execution program for compiling an instruction stream to be executed by a VLIW system computer, said VLIW system computer executing in parallel each instruction element of the VLIW instruction, the compile execution program comprising the steps of:

a process dividing an instruction of the intermediate code format into each slot of the VLIW instruction, and storing the divided instructions to a plurality of intermediate code files;

a serializing process serializing and reading the instructions of the intermediate code format divided and stored in the plurality of intermediate code files;

an instruction scheduling process registering a number, corresponding to each serialized instruction of the intermediate code format, to a writing area of a resource reservation table to produce the resource reservation table;

a paralleled assembly code converting process converting the serialized instructions of the intermediate code format to parallel assembly code depending on an instruction number in the resource reservation table produced in the instruction scheduling process step; and

a paralleled assembly code output process outputting an object program of the paralleled assembly code stream converted by the paralleled assembly code converting step.

12. The recording medium readable by a computer according to claim 11, wherein the intermediate code file does not include an NOP instruction.

13. The recording medium readable by a computer according to claim 12, wherein the converting step further comprises inserting an NOP instruction.

14. The recording medium readable by a computer according to claim 11, further comprising the step of defining the slots as a plurality of slots which is less than the total number of slots of the VLIW instruction, and locating the instructions of the intermediate code format for each slot into at least one intermediate code file.

15. The recording medium readable by a computer according to claim 11, further comprising the step of specifying in an intermediate code file control information for use in specifying the timing for use of a common resource between the instructions of different intermediate code files.